Attention is currently required from: Sean Rhodes.

Marek Maślanka has uploaded this change for review.

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soc/intel/apollolake: Reuse of TCO register definitions

Use the defined TCO registers from the intelpch smbus common header.

BUG=b:314260167
TEST=none

Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6
Signed-off-by: Marek Maslanka <mmaslanka@google.com>
---
M src/soc/intel/apollolake/include/soc/smbus.h
1 file changed, 1 insertion(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/80005/1

diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h
index a87211a..650a7c3 100644
--- a/src/soc/intel/apollolake/include/soc/smbus.h
+++ b/src/soc/intel/apollolake/include/soc/smbus.h
@@ -3,19 +3,7 @@
 #ifndef _SOC_APOLLOLAKE_SMBUS_H_
 #define _SOC_APOLLOLAKE_SMBUS_H_
 
-/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
-#define TCO1_STS			0x04
-#define  TCO_TIMEOUT			(1 << 3)
-#define TCO2_STS			0x06
-#define  TCO2_STS_SECOND_TO		(1 << 1)
-#define  TCO_INTRD_DET			(1 << 0)
-#define TCO1_CNT			0x08
-#define  TCO_LOCK			(1 << 12)
-#define  TCO_TMR_HLT			(1 << 11)
-#define TCO2_CNT			0x0A
-#define  TCO_INTRD_SEL_MASK		(3 << 1)
-#define  TCO_INTRD_SEL_SMI		(1 << 2)
-#define  TCO_INTRD_SEL_INT		(1 << 1)
+#include <intelpch/smbus.h>
 
 #define SMBUS_SLAVE_ADDR		0x24
 

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