[coreboot-gerrit] [S] Change in coreboot[master]: mb/google/rex: Cnfigure `SLP_S0_GATE_R` aka GPP_H14 PIN low

[Subrata Banik (Code Review)]

Attention is currently required from: Kapil Porwal, Ivy Jian, Eric Lai, Utkarsh H Patel, Sukumar Ghorai.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70196 )

Change subject: mb/google/rex: Cnfigure `SLP_S0_GATE_R` aka GPP_H14 PIN low
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Patch Set 3:

(1 comment)

Patchset:

PS3:
> I think we should wait Intel verify this, weird.

I agree that and looking at Brya, this PIN is set to high but if you follow the schematics log, I felt that this PIN should be set to low as SKL_S0_L is the decision maker for the OR gate based on the S0ix flow.