Aamir Bohra uploaded patch set #2 to this change.

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soc/intel/{skylake,cannonlake,icelake}: Correct GPIO IRQ start map

This implementation corrects the GPIO IRQ start map used for ITSS
polarity configuration. The lowest GPIO IRQ mapped in SKL/KBL, CNL,
and ICL is 24. However the PCI controller devices are mapped upto 34,
hence setting the gpio irq snaphot restore from irq#35.

BUG=b:123315212
TEST=[TESTED on CNP(hatch) and SPT(soraka)]
     Verify the ITSS polarity configuration for GPIOs are correctly
     getting restored to original coreboot configuration, after fsp-s
     call in itss_restore_irq_polarities() call.

Change-Id: I3c12e6ca01453da92259f077771c3f4d887aa03d
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
---
M src/soc/intel/cannonlake/include/soc/itss.h
M src/soc/intel/icelake/include/soc/itss.h
M src/soc/intel/skylake/include/soc/itss.h
3 files changed, 21 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31245/2

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