Patrick Rudolph has uploaded this change for review.
mb/lenovo/t520: Add MRC settings in devicetree
Add support for MRC raminit using devicetree settings.
Tested on Lenovo T520.
Change-Id: I58198f3f177a7639675f8a408c1f4e02fcebc50a
---
M src/mainboard/lenovo/t520/Kconfig
M src/mainboard/lenovo/t520/romstage.c
M src/mainboard/lenovo/t520/variants/t520/devicetree.cb
3 files changed, 30 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/32500/1
diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig
index 06f296b..d61f651 100644
--- a/src/mainboard/lenovo/t520/Kconfig
+++ b/src/mainboard/lenovo/t520/Kconfig
@@ -2,7 +2,6 @@
def_bool n
select SYSTEM_TYPE_LAPTOP
select NORTHBRIDGE_INTEL_SANDYBRIDGE
- select USE_NATIVE_RAMINIT
select SOUTHBRIDGE_INTEL_BD82X6X
select EC_LENOVO_PMH7
select EC_LENOVO_H8
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index 96d07fe..8566200 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -20,6 +20,7 @@
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
@@ -95,3 +96,12 @@
void mainboard_config_superio(void)
{
}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+}
+
+int mainboard_should_reset_usb(int s3resume)
+{
+ return !s3resume;
+}
diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb
index cf8e7ce..22db921 100644
--- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb
@@ -36,6 +36,26 @@
register "pci_mmio_size" = "2048"
+ # PEI data
+ register "spd_addresses" = "{ 0xa0, 0x00, 0xa2, 0x00 }"
+ register "ts_addresses" = "{ 0x00, 0x00, 0x00, 0x00 }"
+
+ register "dimm_channel0_disabled" = "2"
+ register "dimm_channel1_disabled" = "2"
+
+ register "max_mem_clock_mhz" = "666" # DDR3-1333
+
+ register "usb_port_config" = "{
+ { 1, 0, 0x0040 }, /* back, towards HDMI plugs */
+ { 1, 0, 0x0040 }, /* back, towards power plug */
+ { 1, 1, 0x0040 }, /* half-width miniPCIe */
+ { 1, 1, 0x0040 }, /* full-width miniPCIe */
+ { 1, 2, 0x0040 }, /* front-panel header */
+ { 1, 2, 0x0040 }, /* front-panel header */
+ { 1, 3, 0x0040 }, /* front connector */
+ }"
+
+
device domain 0 on
device pci 00.0 on end # host bridge
device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M]
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