Patrick Rudolph has uploaded this change for review.

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sb/intel/i82801gx: Use common AHCI

Untested.

Change-Id: I836b43b515545b57eec88bf330da08fdca2902c4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
---
M src/southbridge/intel/i82801gx/Kconfig
M src/southbridge/intel/i82801gx/sata.c
2 files changed, 4 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/37142/1

diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 2d95fc2..b8f8731 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -20,6 +20,7 @@
 	select USE_WATCHDOG_ON_BOOT
 	select HAVE_SMI_HANDLER
 	select COMMON_FADT
+	select SOUTHBRIDGE_INTEL_COMMON_AHCI
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_SPI if BOOT_DEVICE_SPI_FLASH
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 47c35ba..f902013 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -20,6 +20,8 @@
 #include <device/pci.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
+#include <southbridge/intel/common/ahci.h>
+
 #include "chip.h"
 #include "i82801gx.h"
 #include "sata.h"
@@ -154,11 +156,7 @@
 		/* Interrupt Pin is set by D31IP.PIP */
 		pci_write_config8(dev, INTR_LN, 0x0a);
 
-		struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5);
-		if (ahci_res != NULL)
-			/* write AHCI GHC_PI register */
-			write32(res2mmio(ahci_res, 0xc, 0),
-				config->sata_ports_implemented);
+		sb_ahci_init(dev, config->sata_ports_implemented, false, false, 0, false, 0);
 		break;
 	default:
 	case SATA_MODE_IDE_PLAIN:

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