9 comments:
File src/soc/intel/tigerlake/fsp_params_jsl.c:
2019-2020
Done
Patch Set #5, Line 72: enable/disable devices
Nit: I am not seeing any enable/disable device actions besides parsing the devicetree. […]
Done
Patch Set #5, Line 86: MP PPI
Just curious: What is MP PPI?
MP PPI is the coreboot implementation of initializing various CPU specific feature. We publish PPI to FSP and FSP can call coreboot PPI to run feature initialization on all APs.
You can find more details here: https://review.coreboot.org/c/coreboot/+/31841
Patch Set #5, Line 132: if (!dev)
Nit: Use "{" because else block has braces. Just to improve the readability. […]
Done
Patch Set #5, Line 143: PCH_DEV_SLOT_STORAGE
Referring to this CL here: https://review.coreboot. […]
Done
File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
Patch Set #5, Line 16: #include <assert.h>
needed?
Done
#include <soc/gpio_soc_defs.h>
#include <soc/iomap.h>
needed?
Done
Patch Set #5, Line 57: for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
new line […]
Done
/* MbHob */
m_cfg->SkipMbpHob = 0;
not needed.
Done
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