Usha P has uploaded this change for review.

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soc/intel/alderlake: Add support for ADL-N CPU Type

This patch is intended to add Alder Lake-N case
for adl_cpu_type and get_supported_lpm_mask.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d
---
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/include/soc/cpu.h
2 files changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/59836/1

diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 94658c7..be11527 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -168,6 +168,11 @@
 		PCI_DEVICE_ID_INTEL_ADL_S_ID_15,
 	};
 
+	const uint16_t adl_n_mch_ids[] = {
+		PCI_DEVICE_ID_INTEL_ADL_N_ID_1,
+		PCI_DEVICE_ID_INTEL_ADL_N_ID_2,
+	};
+
 	const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT),
 							   PCI_FUNC(SA_DEVFN_ROOT)),
 						   PCI_DEVICE_ID);
@@ -187,6 +192,11 @@
 			return ADL_S;
 	}
 
+	for (size_t i = 0; i < ARRAY_SIZE(adl_n_mch_ids); i++) {
+		if (adl_n_mch_ids[i] == mchid)
+			return ADL_N;
+	}
+
 	return ADL_UNKNOWN;
 }
 
@@ -195,6 +205,7 @@
 	enum adl_cpu_type type = get_adl_cpu_type();
 	switch (type) {
 	case ADL_M: /* fallthrough */
+	case ADL_N:
 	case ADL_P:
 		return LPM_S0i2_0 | LPM_S0i3_0;
 	case ADL_S:
diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h
index 233e0c2..cd6f34f 100644
--- a/src/soc/intel/alderlake/include/soc/cpu.h
+++ b/src/soc/intel/alderlake/include/soc/cpu.h
@@ -22,6 +22,7 @@
 enum adl_cpu_type {
 	ADL_UNKNOWN,
 	ADL_M,
+	ADL_N,
 	ADL_P,
 	ADL_S,
 };

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