Felix Held submitted this change.
nb/intel/sandybridge: move MCHBAR register definitions to sandybridge.h
Change-Id: Ibce9f043d3b3fa9acd297f4130bda7a3c595aaa0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
M src/northbridge/intel/sandybridge/raminit_common.h
M src/northbridge/intel/sandybridge/sandybridge.h
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index 317071c..6bbc8b3 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -149,10 +149,6 @@
#define MAKE_ERR ((channel<<16)|(slotrank<<8)|1)
#define GET_ERR_CHANNEL(x) (x>>16)
-#define MC_BIOS_REQ 0x5e00
-#define MC_BIOS_DATA 0x5e04
-#define PM_PDWN_Config 0x4cb0
-
u8 get_CWL(u32 tCK);
void dram_mrscommands(ramctr_timing * ctrl);
void program_timings(ramctr_timing * ctrl, int channel);
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 6a9c00f..a0fcb10 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -127,8 +127,11 @@
#define MCHBAR32_AND_OR(x, and, or) \
(MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
-#define SSKPD 0x5d14 /* 16bit (scratchpad) */
-#define BIOS_RESET_CPL 0x5da8 /* 8bit */
+#define PM_PDWN_Config 0x4cb0
+#define MC_BIOS_REQ 0x5e00
+#define MC_BIOS_DATA 0x5e04
+#define SSKPD 0x5d14 /* 16bit (scratchpad) */
+#define BIOS_RESET_CPL 0x5da8 /* 8bit */
/*
* EPBAR - Egress Port Root Complex Register Block
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