Elyes Haouas has uploaded this change for review.

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tree: Use boolean for skip_ext_gfx_scan

Change-Id: Icff1b42ceb2e89cc0b2e7abab6743430c635db7b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
---
M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
M src/mainboard/msi/ms7d25/devicetree.cb
M src/mainboard/msi/ms7e06/devicetree.cb
M src/mainboard/protectli/vault_adl_p/devicetree.cb
M src/mainboard/protectli/vault_cml/devicetree.cb
M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
M src/mainboard/system76/addw1/devicetree.cb
M src/mainboard/system76/adl/devicetree.cb
M src/mainboard/system76/bonw14/devicetree.cb
M src/mainboard/system76/cml-u/devicetree.cb
M src/mainboard/system76/gaze15/devicetree.cb
M src/mainboard/system76/oryp5/devicetree.cb
M src/mainboard/system76/oryp6/devicetree.cb
M src/mainboard/system76/rpl/devicetree.cb
M src/mainboard/system76/tgl-h/devicetree.cb
M src/mainboard/system76/tgl-u/devicetree.cb
M src/mainboard/system76/whl-u/devicetree.cb
M src/soc/intel/pantherlake/chip.h
M src/soc/intel/tigerlake/chip.h
22 files changed, 22 insertions(+), 22 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/84155/1

diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
index 11a8749..5e93271 100644
--- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
+++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
@@ -21,7 +21,7 @@
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "SaGv" = "SaGv_Enabled"
-	#register "enable_c6dram" = "1"
+	#register "enable_c6dram" = "true"
 
 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
 	# Serial I/O
diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb
index e874679..3c41f58 100644
--- a/src/mainboard/msi/ms7d25/devicetree.cb
+++ b/src/mainboard/msi/ms7d25/devicetree.cb
@@ -6,7 +6,7 @@
 	# Sagv Configuration
 	register "sagv" = "SaGv_Enabled"
 	register "RMT" = "0"
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 	register "pmc_gpe0_dw0" = "GPP_J"
 	register "pmc_gpe0_dw1" = "GPP_VPGIO"
diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb
index 738c8a3..d087c3f 100644
--- a/src/mainboard/msi/ms7e06/devicetree.cb
+++ b/src/mainboard/msi/ms7e06/devicetree.cb
@@ -6,7 +6,7 @@
 	# Sagv Configuration
 	register "sagv" = "SaGv_Enabled"
 	register "RMT" = "0"
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 	register "pmc_gpe0_dw0" = "GPP_J"
 	register "pmc_gpe0_dw1" = "GPP_VPGIO"
diff --git a/src/mainboard/protectli/vault_adl_p/devicetree.cb b/src/mainboard/protectli/vault_adl_p/devicetree.cb
index f11dc6a..c2959f0 100644
--- a/src/mainboard/protectli/vault_adl_p/devicetree.cb
+++ b/src/mainboard/protectli/vault_adl_p/devicetree.cb
@@ -6,7 +6,7 @@
 	# Sagv Configuration
 	register "sagv" = "SaGv_Enabled"
 	register "RMT" = "0"
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 	register "common_soc_config" = "{
 		// Type-C PD I2C bus
diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb
index 01c5df7..fc06d4c 100644
--- a/src/mainboard/protectli/vault_cml/devicetree.cb
+++ b/src/mainboard/protectli/vault_cml/devicetree.cb
@@ -47,7 +47,7 @@
 
 	register "SkipExtGfxScan" = "1"
 
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[2]" = "1"
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index a555394..87e5849 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -11,7 +11,7 @@
 	# }"
 
 	# FSP Memory
-	register "enable_c6dram"		= "1"
+	register "enable_c6dram"		= "true"
 	register "sagv"				= "SaGv_Enabled"
 
 	# FSP Silicon
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
index df8bd99..570c727 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
@@ -15,7 +15,7 @@
 	}"
 
 	# FSP Memory
-	register "enable_c6dram"		= "1"
+	register "enable_c6dram"		= "true"
 	register "SaGv"				= "SaGv_Enabled"
 
 	# FSP Silicon
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index 1144162..48f6fb3 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -17,7 +17,7 @@
 	# FSP Memory
 	register "CnviBtCore"			= "true"
 	register "CnviBtAudioOffload"		= "1"
-	register "enable_c6dram"		= "1"
+	register "enable_c6dram"		= "true"
 	register "SaGv"				= "SaGv_Enabled"
 
 	# FSP Silicon
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 145dbc2..010567a 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -9,7 +9,7 @@
 	}"
 
 	# FSP Memory
-	register "enable_c6dram"		= "1"
+	register "enable_c6dram"		= "true"
 	register "sagv"				= "SaGv_Enabled"
 
 	# FSP Silicon
diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb
index f5b7a1f..bd8c35f 100644
--- a/src/mainboard/system76/addw1/devicetree.cb
+++ b/src/mainboard/system76/addw1/devicetree.cb
@@ -21,7 +21,7 @@
 	register "eist_enable" = "true"
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
 	# Misc
diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb
index 4e27318..9f144a8 100644
--- a/src/mainboard/system76/adl/devicetree.cb
+++ b/src/mainboard/system76/adl/devicetree.cb
@@ -14,7 +14,7 @@
 	register "eist_enable" = "true"
 
 	# Enable C6 DRAM
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 	# Thermal
 	register "tcc_offset" = "8"
diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb
index 3a99ab4..56d50db 100644
--- a/src/mainboard/system76/bonw14/devicetree.cb
+++ b/src/mainboard/system76/bonw14/devicetree.cb
@@ -21,7 +21,7 @@
 	register "eist_enable" = "true"
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
 	# Serial I/O
diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb
index ed0a520..0c87d3a 100644
--- a/src/mainboard/system76/cml-u/devicetree.cb
+++ b/src/mainboard/system76/cml-u/devicetree.cb
@@ -22,7 +22,7 @@
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "SaGv" = "SaGv_Enabled"
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
 	# Serial I/O
diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb
index 5760e66..565c7f7 100644
--- a/src/mainboard/system76/gaze15/devicetree.cb
+++ b/src/mainboard/system76/gaze15/devicetree.cb
@@ -21,7 +21,7 @@
 	register "eist_enable" = "true"
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
 	# Misc
diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb
index cc3c619..bf4b89a 100644
--- a/src/mainboard/system76/oryp5/devicetree.cb
+++ b/src/mainboard/system76/oryp5/devicetree.cb
@@ -21,7 +21,7 @@
 	register "eist_enable" = "true"
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
 	# Serial I/O
diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb
index 7e3ef0c..cdc50e9 100644
--- a/src/mainboard/system76/oryp6/devicetree.cb
+++ b/src/mainboard/system76/oryp6/devicetree.cb
@@ -21,7 +21,7 @@
 	register "eist_enable" = "true"
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
 	# Serial I/O
diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb
index dd4d597..b5926ef 100644
--- a/src/mainboard/system76/rpl/devicetree.cb
+++ b/src/mainboard/system76/rpl/devicetree.cb
@@ -14,7 +14,7 @@
 	register "eist_enable" = "true"
 
 	# Enable C6 DRAM
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 	# Thermal
 	register "tcc_offset" = "8"
diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb
index 2bda9dc..acf50d1 100644
--- a/src/mainboard/system76/tgl-h/devicetree.cb
+++ b/src/mainboard/system76/tgl-h/devicetree.cb
@@ -27,7 +27,7 @@
 
 # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
 	# Enable C6 DRAM
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 # FSP Silicon (soc/intel/tigerlake/fsp_params.c)
 	# Acoustic settings
diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb
index d96249d..67bdf8e 100644
--- a/src/mainboard/system76/tgl-u/devicetree.cb
+++ b/src/mainboard/system76/tgl-u/devicetree.cb
@@ -19,7 +19,7 @@
 
 # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
 	# Enable C6 DRAM
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 	# System Agent dynamic frequency support
 	register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb
index 1c5d720..9fbc526 100644
--- a/src/mainboard/system76/whl-u/devicetree.cb
+++ b/src/mainboard/system76/whl-u/devicetree.cb
@@ -22,7 +22,7 @@
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "SaGv" = "SaGv_Enabled"
-	register "enable_c6dram" = "1"
+	register "enable_c6dram" = "true"
 
 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
 	# Serial I/O
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index d1dbe44..3872916 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -201,7 +201,7 @@
 	uint8_t eist_enable;
 
 	/* Enable C6 DRAM */
-	uint8_t enable_c6dram;
+	bool enable_c6dram;
 	uint8_t PmTimerDisabled;
 	/*
 	 * SerialIO device mode selection:
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 97fd275..4d4e2a1 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -288,7 +288,7 @@
 	bool eist_enable;
 
 	/* Enable C6 DRAM */
-	uint8_t enable_c6dram;
+	bool enable_c6dram;
 
 	/*
 	 * SerialIO device mode selection:

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