Patrick Rudolph has uploaded this change for review.
[WIP]acpi: Get rid of boilerplate FADT
Still not done....
Needs test on windows and Linux on all affected platforms, that is every x86 platform.
Change-Id: If58fcf9a1c39c159dfa08339cb931e552d499747
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
M src/arch/x86/acpi.c
M src/arch/x86/include/arch/acpi.h
M src/soc/intel/apollolake/acpi.c
M src/soc/intel/cannonlake/acpi.c
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/skylake/acpi.c
M src/soc/intel/xeon_sp/cpx/acpi.c
M src/soc/intel/xeon_sp/skx/acpi.c
M src/southbridge/amd/cimx/sb800/fadt.c
M src/southbridge/amd/pi/hudson/fadt.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/i82371eb/fadt.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/lynxpoint/lpc.c
17 files changed, 407 insertions(+), 1,080 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/40036/1
diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
index e4932be..d540721 100644
--- a/src/arch/x86/acpi.c
+++ b/src/arch/x86/acpi.c
@@ -1249,6 +1249,17 @@
fadt->sleep_control_reg.bit_width = 8;
fadt->sleep_status_reg.bit_width = 8;
+ if (CONFIG(ARCH_X86)) {
+ /* Set x86 defaults. A SoC can still overwrite those. */
+ fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->reset_reg.addrl = SYS_RESET;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = RST_CPU | SYS_RST;
+ }
acpi_fill_fadt(fadt);
header->checksum =
@@ -1256,6 +1267,130 @@
}
#endif
+static void acpi_update_access_size(acpi_addr_t *reg)
+{
+ switch (DIV_ROUND_UP(reg->bit_width, 8)) {
+ case 0:
+ reg->access_size = ACPI_ACCESS_SIZE_UNDEFINED;
+ default:
+ case 1:
+ reg->access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ break;
+ case 2:
+ reg->access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ break;
+ case 4:
+ reg->access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ break;
+ case 8:
+ reg->access_size = ACPI_ACCESS_SIZE_QDWORD_ACCESS;
+ break;
+ }
+}
+
+void acpi_fill_fadt_x86_pm(acpi_fadt_t *fadt,
+ u32 pm1a_evt_blk,
+ u32 pm1b_evt_blk,
+ u32 pm1a_cnt_blk,
+ u32 pm1b_cnt_blk,
+ u32 pm2_cnt_blk,
+ u32 pm_tmr_blk,
+ u32 gpe0_blk,
+ u32 gpe1_blk,
+ u8 pm1_evt_len,
+ u8 pm1_cnt_len,
+ u8 pm2_cnt_len,
+ u8 pm_tmr_len,
+ u8 gpe0_blk_len,
+ u8 gpe1_blk_len,
+ u8 gpe1_base)
+{
+ fadt->pm1a_evt_blk = pm1a_evt_blk;
+ fadt->pm1b_evt_blk = pm1b_evt_blk;
+ fadt->pm1a_cnt_blk = pm1a_cnt_blk;
+ fadt->pm1b_cnt_blk = pm1b_cnt_blk;
+ fadt->pm2_cnt_blk = pm2_cnt_blk;
+ fadt->pm_tmr_blk = pm_tmr_blk;
+ fadt->gpe0_blk = gpe0_blk;
+ fadt->gpe1_blk = gpe1_blk;
+ fadt->gpe1_base = gpe1_base;
+
+ fadt->pm1_evt_len = pm1_evt_len;
+ fadt->pm1_cnt_len = pm1_cnt_len;
+ fadt->pm2_cnt_len = pm2_cnt_len;
+ fadt->pm_tmr_len = pm_tmr_len;
+ fadt->gpe0_blk_len = gpe0_blk_len;
+ fadt->gpe1_blk_len = gpe1_blk_len;
+
+ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ fadt->x_pm1a_evt_blk.addrl = pm1a_evt_blk;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+ acpi_update_access_size(&fadt->x_pm1a_evt_blk);
+
+ fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1b_evt_blk.bit_width = pm1_evt_len * 8;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ fadt->x_pm1b_evt_blk.addrl = pm1b_evt_blk;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+ acpi_update_access_size(&fadt->x_pm1b_evt_blk);
+
+ fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1a_cnt_blk.bit_width = pm1_cnt_len * 8;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ fadt->x_pm1a_cnt_blk.addrl = pm1a_cnt_blk;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+ acpi_update_access_size(&fadt->x_pm1a_cnt_blk);
+
+ fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1b_cnt_blk.bit_width = pm1_cnt_len * 8;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ fadt->x_pm1b_cnt_blk.addrl = pm1b_cnt_blk;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+ acpi_update_access_size(&fadt->x_pm1b_cnt_blk);
+
+ fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm2_cnt_blk.bit_width = pm2_cnt_len * 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->x_pm2_cnt_blk.addrl = pm2_cnt_blk;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+ acpi_update_access_size(&fadt->x_pm2_cnt_blk);
+
+ fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm_tmr_blk.bit_width = pm_tmr_len * 8;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm_tmr_blk.addrl = pm_tmr_blk;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+ acpi_update_access_size(&fadt->x_pm_tmr_blk);
+
+ /*
+ * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5.
+ * The bit_width field intentionally overflows here.
+ * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which
+ * seems to work fine on Linux 5.0 and Windows 10.
+ */
+ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_gpe0_blk.bit_width = gpe0_blk_len * 8;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->x_gpe0_blk.addrl = gpe0_blk;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_gpe1_blk.bit_width = gpe1_blk_len * 8;
+ fadt->x_gpe1_blk.bit_offset = gpe1_base * 8;
+ fadt->x_gpe1_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->x_gpe1_blk.addrl = gpe1_blk;
+ fadt->x_gpe1_blk.addrh = 0x0;
+}
+
unsigned long __weak fw_cfg_acpi_tables(unsigned long start)
{
return 0;
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 4351678..107ad86 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -844,6 +844,25 @@
#if CONFIG(COMMON_FADT)
void acpi_fill_fadt(acpi_fadt_t *fadt);
#endif
+/**
+ * Fill in ACPI FADT fields used by a generic x86 platform.
+ * That is all PM* and GPE* are located in IO space.
+ */
+void acpi_fill_fadt_x86_pm(acpi_fadt_t *fadt,
+ u32 pm1a_evt_blk,
+ u32 pm1b_evt_blk,
+ u32 pm1a_cnt_blk,
+ u32 pm1b_cnt_blk,
+ u32 pm2_cnt_blk,
+ u32 pm_tmr_blk,
+ u32 gpe0_blk,
+ u32 gpe1_blk,
+ u8 pm1_evt_len,
+ u8 pm1_cnt_len,
+ u8 pm2_cnt_len,
+ u8 pm_tmr_len,
+ u8 gpe0_blk_len,
+ u8 gpe1_blk_len);
void update_ssdt(void *ssdt);
void update_ssdtx(void *ssdtx, int i);
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index fbfe33f..ef1c01d 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -152,10 +152,9 @@
void soc_fill_fadt(acpi_fadt_t *fadt)
{
const struct soc_intel_apollolake_config *cfg;
+ const uint16_t pmbase = ACPI_BASE_ADDRESS;
cfg = config_of_soc();
- fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR;
-
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
@@ -164,13 +163,25 @@
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
- fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
-
if (cfg->lpss_s0ix_enable)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
+
+ acpi_fill_fadt_x86_pm(fadt,
+ pmbase + PM1_STS,
+ 0,
+ pmbase + PM1_CNT,
+ 0,
+ 0,
+ pmbase + PM1_TMR,
+ pmbase + GPE0_STS(0),
+ 0,
+ 4,
+ 2,
+ 0,
+ 4,
+ 2 * GPE0_REG_MAX,
+ 0,
+ 0);
}
static unsigned long soc_fill_dmar(unsigned long current)
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 84659c9..490cabc 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -176,17 +176,25 @@
const struct soc_intel_cannonlake_config *config;
config = config_of_soc();
- fadt->pm_tmr_blk = pmbase + PM1_TMR;
- fadt->pm_tmr_len = 4;
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
if (config->s0ix_enable)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
+
+ acpi_fill_fadt_x86_pm(fadt,
+ pmbase + PM1_STS,
+ 0,
+ pmbase + PM1_CNT,
+ 0,
+ 0,
+ pmbase + PM1_TMR,
+ pmbase + GPE0_STS(0),
+ 0,
+ 4,
+ 2,
+ 0,
+ 4,
+ 2 * GPE0_REG_MAX,
+ 0,
+ 0);
}
uint32_t soc_read_sci_irq_select(void)
{
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index fe127a2..c729cc8 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -178,6 +178,17 @@
fadt->x_gpe1_blk.space_id = 1;
+
+ fadt->pm1a_evt_blk = pmbase + PM1_STS;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
+ fadt->pm1b_cnt_blk = 0x0;
+
+ fadt->gpe0_blk = pmbase + GPE0_STS(0);
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+
soc_fill_fadt(fadt);
}
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c
index d3e2853..fd8b934 100644
--- a/src/soc/intel/denverton_ns/acpi.c
+++ b/src/soc/intel/denverton_ns/acpi.c
@@ -132,7 +132,7 @@
void soc_fill_fadt(acpi_fadt_t *fadt)
{
- u16 pmbase = get_pmbase();
+ const u16 pmbase = get_pmbase();
/* System Management */
if (!CONFIG(HAVE_SMI_HANDLER)) {
@@ -141,17 +141,6 @@
fadt->acpi_disable = 0x00;
}
- /* Power Control */
- fadt->pm2_cnt_blk = pmbase + PM2_CNT;
- fadt->pm_tmr_blk = pmbase + PM1_TMR;
- fadt->gpe1_blk = 0;
-
- /* Control Registers - Length */
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 8;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
@@ -171,75 +160,22 @@
ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE |
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
- /* Reset Register */
- fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->reset_reg.addrl = 0xCF9;
- fadt->reset_reg.addrh = 0x00;
- fadt->reset_value = 6;
-
- /* PM1 Status & PM1 Enable */
- fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
- fadt->x_pm1a_evt_blk.addrh = 0x00;
-
- fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.access_size = 0;
- fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
- fadt->x_pm1b_evt_blk.addrh = 0x00;
-
- /* PM1 Control Registers */
- fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
- fadt->x_pm1a_cnt_blk.addrh = 0x00;
-
- fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.access_size = 0;
- fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
- fadt->x_pm1b_cnt_blk.addrh = 0x00;
-
- /* PM2 Control Registers */
- fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm2_cnt_blk.bit_width = 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
- fadt->x_pm2_cnt_blk.addrh = 0x00;
-
- /* PM1 Timer Register */
- fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
- fadt->x_pm_tmr_blk.addrh = 0x00;
-
- /* General-Purpose Event Registers */
- fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
- fadt->x_gpe0_blk.addrh = 0x00;
-
- fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
- fadt->x_gpe1_blk.addrh = 0x00;
+ acpi_fill_fadt_x86_pm(fadt,
+ pmbase + PM1_STS,
+ 0,
+ pmbase + PM1_CNT,
+ 0,
+ pmbase + PM2_CNT,
+ pmbase + PM1_TMR,
+ pmbase + GPE0_STS(0),
+ 0,
+ 4,
+ 2,
+ 1,
+ 4,
+ 2 * GPE0_REG_MAX * sizeof(uint32_t),
+ 0,
+ 0);
motherboard_fill_fadt(fadt);
}
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 550dd56..9e24017 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -234,8 +234,6 @@
const uint16_t pmbase = ACPI_BASE_ADDRESS;
config_t *config = config_of_soc();
- fadt->header.revision = get_acpi_table_revision(FADT);
-
fadt->sci_int = acpi_sci_irq();
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
@@ -243,23 +241,6 @@
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0;
- fadt->pm1a_evt_blk = pmbase + PM1_STS;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = pmbase + PM2_CNT;
- fadt->pm_tmr_blk = pmbase + PM1_TMR;
- fadt->gpe0_blk = pmbase + GPE0_STS(0);
- fadt->gpe1_blk = 0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */
- fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
@@ -282,75 +263,22 @@
if (config->s0ix_enable)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0;
- fadt->reset_value = 6;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.access_size = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.access_size = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- /*
- * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5.
- * The bit_width field intentionally overflows here.
- * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which
- * seems to work fine on Linux 5.0 and Windows 10.
- */
- fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
- fadt->x_gpe0_blk.addrh = 0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
+ acpi_fill_fadt_x86_pm(fadt,
+ pmbase + PM1_STS,
+ 0,
+ pmbase + PM1_CNT,
+ 0,
+ pmbase + PM2_CNT,
+ pmbase + PM1_TMR,
+ pmbase + GPE0_STS(0),
+ 0,
+ 4,
+ 2,
+ 1,
+ 4,
+ 2 * GPE0_REG_MAX * sizeof(uint32_t),
+ 0,
+ 0);
}
static void write_c_state_entries(acpi_cstate_t *map, const int *set, size_t max_c_state)
diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c
index 48ad374..1688ae3 100644
--- a/src/soc/intel/xeon_sp/cpx/acpi.c
+++ b/src/soc/intel/xeon_sp/cpx/acpi.c
@@ -108,19 +108,6 @@
fadt->header.revision = get_acpi_table_revision(FADT);
fadt->sci_int = SCI_INT_NUM;
- fadt->pm1a_evt_blk = pmbase + PM1_STS;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
- fadt->pm1b_cnt_blk = 0x0;
-
- fadt->gpe0_blk = pmbase + GPE0_STS(0);
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
-
- /* GPE0 STS/EN pairs each 32 bits wide. */
- fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
-
fadt->flush_size = 0x400; /* twice of cache size */
fadt->flush_stride = 0x10; /* Cache line width */
fadt->duty_offset = 1;
@@ -129,26 +116,6 @@
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED |
ACPI_FADT_RESET_REGISTER | ACPI_FADT_PLATFORM_CLOCK;
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.addrl = RST_CNT;
- fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->reset_value = RST_CPU | SYS_RST;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
- fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
-
- fadt->x_gpe1_blk.space_id = 1;
-
if (CONFIG(HAVE_SMI_HANDLER)) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
@@ -165,18 +132,19 @@
fadt->cst_cnt = 0;
}
- /* General-Purpose Event Registers */
- fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
- fadt->x_gpe0_blk.addrh = 0;
-
- fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0;
- fadt->x_gpe1_blk.addrh = 0;
+ acpi_fill_fadt_x86_pm(fadt,
+ pmbase + PM1_STS,
+ 0,
+ pmbase + PM1_CNT,
+ 0,
+ 0,
+ 0,
+ pmbase + GPE0_STS(0),
+ 0,
+ 4,
+ 2,
+ 0,
+ 0,
+ 2 * GPE0_REG_MAX * sizeof(uint32_t),
+ 0);
}
diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c
index e9edc99..aab93b4 100644
--- a/src/soc/intel/xeon_sp/skx/acpi.c
+++ b/src/soc/intel/xeon_sp/skx/acpi.c
@@ -247,18 +247,6 @@
fadt->acpi_disable = 0x00;
}
- /* Power Control */
- fadt->pm2_cnt_blk = pmbase + PM2_CNT;
- fadt->pm_tmr_blk = pmbase + PM1_TMR;
- fadt->gpe1_blk = 0;
-
- /* Control Registers - Length */
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */
- fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
@@ -278,75 +266,21 @@
ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE |
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
- /* Reset Register */
- fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->reset_reg.addrl = 0xCF9;
- fadt->reset_reg.addrh = 0x00;
- fadt->reset_value = 6;
-
- /* PM1 Status & PM1 Enable */
- fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
- fadt->x_pm1a_evt_blk.addrh = 0x00;
-
- fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.access_size = 0;
- fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
- fadt->x_pm1b_evt_blk.addrh = 0x00;
-
- /* PM1 Control Registers */
- fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
- fadt->x_pm1a_cnt_blk.addrh = 0x00;
-
- fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.access_size = 0;
- fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
- fadt->x_pm1b_cnt_blk.addrh = 0x00;
-
- /* PM2 Control Registers */
- fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm2_cnt_blk.bit_width = 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
- fadt->x_pm2_cnt_blk.addrh = 0x00;
-
- /* PM1 Timer Register */
- fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
- fadt->x_pm_tmr_blk.addrh = 0x00;
-
- /* General-Purpose Event Registers */
- fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
- fadt->x_gpe0_blk.addrh = 0x00;
-
- fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
- fadt->x_gpe1_blk.addrh = 0x00;
+ acpi_fill_fadt_x86_pm(fadt,
+ pmbase + PM1_STS,
+ 0,
+ pmbase + PM1_CNT,
+ 0,
+ pmbase + PM2_CNT,
+ pmbase + PM1_TMR,
+ pmbase + GPE0_STS(0),
+ 0,
+ 4,
+ 2,
+ 1,
+ 4,
+ 2 * GPE0_REG_MAX * sizeof(uint32_t),
+ 0);
motherboard_fill_fadt(fadt);
}
@@ -355,8 +289,6 @@
{
const uint16_t pmbase = ACPI_BASE_ADDRESS;
- fadt->header.revision = get_acpi_table_revision(FADT);
-
fadt->sci_int = acpi_sci_irq();
/*
TODO: enabled SMM mode switch when SMM handlers are set up.
@@ -370,23 +302,6 @@
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0;
- fadt->pm1a_evt_blk = pmbase + PM1_STS;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = pmbase + PM2_CNT;
- fadt->pm_tmr_blk = pmbase + PM1_TMR;
- fadt->gpe0_blk = pmbase + GPE0_STS(0);
- fadt->gpe1_blk = 0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */
- fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
@@ -406,69 +321,21 @@
ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0;
- fadt->reset_value = 6;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.access_size = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.access_size = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
- fadt->x_gpe0_blk.addrh = 0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
+ acpi_fill_fadt_x86_pm(fadt,
+ pmbase + PM1_STS,
+ 0,
+ pmbase + PM1_CNT,
+ 0,
+ pmbase + PM2_CNT,
+ pmbase + PM1_TMR,
+ pmbase + GPE0_STS(0),
+ 0,
+ 4,
+ 2,
+ 1,
+ 4,
+ 2 * GPE0_REG_MAX * sizeof(uint32_t),
+ 0);
soc_fill_fadt(fadt);
}
diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c
index 08fbecb..5b3fee6 100644
--- a/src/southbridge/amd/cimx/sb800/fadt.c
+++ b/src/southbridge/amd/cimx/sb800/fadt.c
@@ -104,22 +104,6 @@
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */
- fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
- fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
- fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
- fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
- fadt->gpe0_blk = GPE0_BLK_ADDRESS;
- fadt->gpe1_blk = 0; /* No gpe1 block in hudson1 */
-
- fadt->pm1_evt_len = 4; /* 32 bits */
- fadt->pm1_cnt_len = 2; /* 16 bits */
- fadt->pm2_cnt_len = 1; /* 8 bits */
- fadt->pm_tmr_len = 4; /* 32 bits */
- fadt->gpe0_blk_len = 8; /* 64 bits */
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
@@ -143,17 +127,6 @@
ACPI_FADT_S4_RTC_VALID |
ACPI_FADT_REMOTE_POWER_ON;
- /* Format is from 5.2.3.1: Generic Address Structure */
- /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */
- /* 8 bit write of value 0x06 to 0xCF9 in IO space */
- fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0x0;
- fadt->reset_value = 6;
-
fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */
fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */
@@ -162,66 +135,22 @@
fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff;
fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32;
- fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.access_size = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-
- fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.access_size = 0;
- fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.access_size = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm2_cnt_blk.bit_width = 8; /* Hudson 1 Pm2Control is 8 bits */
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
-
- fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
- fadt->x_gpe0_blk.addrh = 0x0;
-
-
- fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0;
- fadt->x_gpe1_blk.addrh = 0x0;
+ acpi_fill_fadt_x86_pm(fadt,
+ PM1_EVT_BLK_ADDRESS,
+ 0x0000,
+ PM1_CNT_BLK_ADDRESS,
+ 0x0000,
+ ACPI_PMA_CNT_BLK_ADDRESS,
+ PM1_TMR_BLK_ADDRESS,
+ GPE0_BLK_ADDRESS,
+ 0,
+ 4,
+ 2,
+ 1,
+ 4,
+ 2 * sizeof(uint32_t),
+ 0,
+ 0);
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c
index 8573c8b..b7192f9 100644
--- a/src/southbridge/amd/pi/hudson/fadt.c
+++ b/src/southbridge/amd/pi/hudson/fadt.c
@@ -77,23 +77,6 @@
fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */
}
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
- fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
- fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = 0x0000;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
- fadt->gpe1_blk = 0x0000; /* No gpe1 block in hudson */
-
- fadt->pm1_evt_len = 4; /* 32 bits */
- fadt->pm1_cnt_len = 2; /* 16 bits */
- fadt->pm2_cnt_len = 0;
- fadt->pm_tmr_len = 4; /* 32 bits */
- fadt->gpe0_blk_len = 8; /* 64 bits */
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
-
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
@@ -116,89 +99,31 @@
ACPI_FADT_S4_RTC_VALID |
ACPI_FADT_REMOTE_POWER_ON;
- /* Format is from 5.2.3.1: Generic Address Structure */
- /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */
- /* 8 bit write of value 0x06 to 0xCF9 in IO space */
- fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 6;
-
- fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */
- fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */
-
fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32) dsdt;
fadt->x_dsdt_h = 0;
- fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.access_size = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-
- fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.access_size = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.access_size = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
/*
* Note: Under this current AMD C state implementation, this is no longer
* used and should not be reported to OS.
*/
- fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_pm2_cnt_blk.addrl = 0;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
-
- fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
- fadt->x_gpe0_blk.addrh = 0x0;
-
-
- fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0;
- fadt->x_gpe1_blk.addrh = 0x0;
+ acpi_fill_fadt_x86_pm(fadt,
+ ACPI_PM_EVT_BLK,
+ 0x0000,
+ ACPI_PM1_CNT_BLK,
+ 0x0000,
+ 0x0000,
+ ACPI_PM_TMR_BLK,
+ ACPI_GPE0_BLK,
+ 0x0000,
+ 4,
+ 2,
+ 0,
+ 4,
+ 2 * sizeof(uint32_t),
+ 0,
+ 0);
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
}
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 46ab5fc..9aec7db 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -717,22 +717,6 @@
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0;
- fadt->pm1a_evt_blk = pmbase;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + 0x4;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = pmbase + 0x50;
- fadt->pm_tmr_blk = pmbase + 0x8;
- fadt->gpe0_blk = pmbase + 0x20;
- fadt->gpe1_blk = 0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 16;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
c2_latency = chip->c2_latency;
if (!c2_latency) {
@@ -765,70 +749,22 @@
fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED;
}
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0;
-
- fadt->reset_value = 6;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm1a_evt_blk.addrl = pmbase;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.access_size = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.access_size = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 128;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_gpe0_blk.addrl = pmbase + 0x20;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
+ acpi_fill_fadt_x86_pm(fadt,
+ pmbase,
+ 0x0,
+ pmbase + 0x4,
+ 0x0,
+ pmbase + 0x50,
+ pmbase + 0x8,
+ pmbase + 0x20,
+ 0,
+ 4,
+ 2,
+ 1,
+ 4,
+ 2 * 2 * sizeof(uint32_t),
+ 0,
+ 0);
}
static const char *lpc_acpi_name(const struct device *dev)
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index db1071a..4b27b97 100644
--- a/src/southbridge/intel/i82371eb/fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
@@ -52,25 +52,6 @@
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0x0;
- fadt->pm1a_evt_blk = DEFAULT_PMBASE;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL;
- fadt->pm1b_cnt_blk = 0x0;
-
- fadt->pm2_cnt_blk = 0;
- fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR;
- fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS;
- fadt->gpe1_blk = 0x0;
- fadt->gpe1_base = 0;
- fadt->gpe1_blk_len = 0;
-
- /* *_len define register width in bytes */
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 0; /* not supported */
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 4;
-
fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */
fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */
fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */
@@ -141,74 +122,22 @@
*/
fadt->flags = 0xa5;
- fadt->reset_reg.space_id = 0;
- fadt->reset_reg.bit_width = 0;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.access_size = 0;
- fadt->reset_reg.addrl = 0x0;
- fadt->reset_reg.addrh = 0x0;
- fadt->reset_value = 0;
-
- fadt->x_firmware_ctl_l = (uintptr_t)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (uintptr_t)dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.access_size = 0;
- fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
- fadt->x_gpe1_blk.addrh = 0x0;
+ acpi_fill_fadt_x86_pm(fadt,
+ DEFAULT_PMBASE,
+ 0,
+ DEFAULT_PMBASE + PMCNTRL,
+ 0,
+ 0,
+ DEFAULT_PMBASE + PMTMR,
+ DEFAULT_PMBASE + GPSTS,
+ 0,
+ 4,
+ 2,
+ 0,
+ 4,
+ 2 * sizeof(uint16_t),
+ 0,
+ 0);
header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
}
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 743dbba..8977228 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -452,87 +452,6 @@
config_t *chip = dev->chip_info;
u16 pmbase = lpc_get_pmbase();
- fadt->pm1a_evt_blk = pmbase;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = pmbase + PM2_CNT;
- fadt->pm_tmr_blk = pmbase + PM1_TMR;
- fadt->gpe0_blk = pmbase + GPE0_STS;
- fadt->gpe1_blk = 0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 8;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0;
-
- fadt->reset_value = 6;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm1a_evt_blk.addrl = pmbase;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 0;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.access_size = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 0;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.access_size = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 64;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 0;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->century = 0x32;
@@ -562,6 +481,23 @@
| ACPI_FADT_C2_MP_SUPPORTED);
if (chip->docking_supported)
fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
+
+ acpi_fill_fadt_x86_pm(fadt,
+ pmbase,
+ 0,
+ pmbase + PM1_CNT,
+ 0,
+ pmbase + PM2_CNT,
+ pmbase + PM1_TMR,
+ pmbase + GPE0_STS,
+ 0,
+ 4,
+ 2,
+ 1,
+ 4,
+ 2 * sizeof(uint32_t),
+ 0,
+ 0);
}
static void i82801gx_lpc_read_resources(struct device *dev)
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index e3fdde7..ae40a42 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -460,86 +460,6 @@
config_t *chip = dev->chip_info;
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
- fadt->pm1a_evt_blk = pmbase;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + 0x4;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = pmbase + 0x50;
- fadt->pm_tmr_blk = pmbase + 0x8;
- fadt->gpe0_blk = pmbase + 0x20;
- fadt->gpe1_blk = 0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 16;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0;
- fadt->reset_value = 6;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm1a_evt_blk.addrl = pmbase;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 0;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.access_size = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 0;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.access_size = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 128;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_gpe0_blk.addrl = pmbase + 0x20;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 0;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->century = 0x32;
@@ -569,6 +489,23 @@
| ACPI_FADT_C2_MP_SUPPORTED);
if (chip->docking_supported)
fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
+
+ acpi_fill_fadt_x86_pm(fadt,
+ pmbase,
+ 0,
+ pmbase + 0x4,
+ 0,
+ pmbase + 0x50,
+ pmbase + 0x8,
+ pmbase + 0x20,
+ 0,
+ 4,
+ 2,
+ 1,
+ 4,
+ 2 * 2 * sizeof(uint32_t),
+ 0,
+ 0);
}
static void i82801jx_lpc_read_resources(struct device *dev)
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 0062e09..29a263a 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -617,22 +617,6 @@
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0;
- fadt->pm1a_evt_blk = pmbase;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + 0x4;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = pmbase + 0x50;
- fadt->pm_tmr_blk = pmbase + 0x8;
- fadt->gpe0_blk = pmbase + 0x20;
- fadt->gpe1_blk = 0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 16;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
c2_latency = chip->c2_latency;
if (!c2_latency) {
@@ -664,70 +648,22 @@
fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED;
}
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0;
-
- fadt->reset_value = 6;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm1a_evt_blk.addrl = pmbase;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.access_size = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.access_size = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 128;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_gpe0_blk.addrl = pmbase + 0x20;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
+ acpi_fill_fadt_x86_pm(fadt,
+ pmbase,
+ 0,
+ pmbase + 0x4,
+ 0,
+ pmbase + 0x50,
+ pmbase + 0x8,
+ pmbase + 0x20,
+ 0,
+ 4,
+ 2,
+ 1,
+ 4,
+ 2 * 2 * sizeof(uint32_t),
+ 0,
+ 0);
}
static const char *lpc_acpi_name(const struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 0bfca35..589c4fa 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -767,35 +767,6 @@
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0;
- fadt->pm1a_evt_blk = pmbase + PM1_STS;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = pmbase + PM2_CNT;
- fadt->pm_tmr_blk = pmbase + PM1_TMR;
- if (pch_is_lp())
- fadt->gpe0_blk = pmbase + LP_GPE0_STS_1;
- else
- fadt->gpe0_blk = pmbase + GPE0_STS;
- fadt->gpe1_blk = 0;
-
- /*
- * Some of the lengths here are doubled. This is because they describe
- * blocks containing two registers, where the size of each register
- * is found by halving the block length. See Table 5-34 and section
- * 4.8.3 of the ACPI specification for details.
- */
- fadt->pm1_evt_len = 2 * 2;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- if (pch_is_lp())
- fadt->gpe0_blk_len = 2 * 16;
- else
- fadt->gpe0_blk_len = 2 * 8;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
-
fadt->cst_cnt = 0;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
@@ -820,76 +791,21 @@
if (cfg->docking_supported)
fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
- fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0;
-
- fadt->reset_value = 6;
-
- fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1a_evt_blk.bit_width = 2 * 16;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.access_size = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.access_size = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm2_cnt_blk.bit_width = 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- /*
- * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5.
- * The bit_width field intentionally overflows here.
- * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which
- * seems to work fine on Linux 5.0 and Windows 10.
- */
- fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
+ acpi_fill_fadt_x86_pm(fadt,
+ pmbase + PM1_STS,
+ 0,
+ pmbase + PM1_CNT,
+ 0,
+ pmbase + PM2_CNT,
+ pmbase + PM1_TMR,
+ pch_is_lp() ? (pmbase + LP_GPE0_STS_1) : (pmbase + GPE0_STS),
+ 0,
+ 4,
+ 2,
+ 1,
+ 4,
+ pch_is_lp() ? (2 * 4 * sizeof(uint32_t)) : (2 * 2 * sizeof(uint32_t)),
+ 0);
}
static const char *lpc_acpi_name(const struct device *dev)
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