58 comments:
File src/soc/mediatek/mt8192/pll.c:
Patch Set #1, Line 114: MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, clk_cfg_0_set, clk_cfg_0_clr, 24, 3, clk_cfg_update, 3),
line over 96 characters
Patch Set #1, Line 118: MUX_UPD(TOP_IMG1_SEL, clk_cfg_1, clk_cfg_1_set, clk_cfg_1_clr, 16, 4, clk_cfg_update, 6),
line over 96 characters
Patch Set #1, Line 119: MUX_UPD(TOP_IMG2_SEL, clk_cfg_1, clk_cfg_1_set, clk_cfg_1_clr, 24, 4, clk_cfg_update, 7),
line over 96 characters
Patch Set #1, Line 123: MUX_UPD(TOP_CAM_SEL, clk_cfg_2, clk_cfg_2_set, clk_cfg_2_clr, 16, 4, clk_cfg_update, 10),
line over 96 characters
Patch Set #1, Line 124: MUX_UPD(TOP_CCU_SEL, clk_cfg_2, clk_cfg_2_set, clk_cfg_2_clr, 24, 4, clk_cfg_update, 11),
line over 96 characters
Patch Set #1, Line 127: MUX_UPD(TOP_DSP1_SEL, clk_cfg_3, clk_cfg_3_set, clk_cfg_3_clr, 8, 3, clk_cfg_update, 13),
line over 96 characters
Patch Set #1, Line 129: MUX_UPD(TOP_DSP2_SEL, clk_cfg_3, clk_cfg_3_set, clk_cfg_3_clr, 16, 3, clk_cfg_update, 14),
line over 96 characters
Patch Set #1, Line 131: MUX_UPD(TOP_DSP5_SEL, clk_cfg_3, clk_cfg_3_set, clk_cfg_3_clr, 24, 3, clk_cfg_update, 15),
line over 96 characters
Patch Set #1, Line 134: MUX_UPD(TOP_DSP7_SEL, clk_cfg_4, clk_cfg_4_set, clk_cfg_4_clr, 0, 3, clk_cfg_update, 16),
line over 96 characters
Patch Set #1, Line 135: MUX_UPD(TOP_IPU_IF_SEL, clk_cfg_4, clk_cfg_4_set, clk_cfg_4_clr, 8, 3, clk_cfg_update, 17),
line over 96 characters
Patch Set #1, Line 136: MUX_UPD(TOP_MFG_REF_SEL, clk_cfg_4, clk_cfg_4_set, clk_cfg_4_clr, 16, 2, clk_cfg_update, 18),
line over 96 characters
Patch Set #1, Line 138: MUX_UPD(TOP_CAMTG_SEL, clk_cfg_4, clk_cfg_4_set, clk_cfg_4_clr, 24, 3, clk_cfg_update, 19),
line over 96 characters
Patch Set #1, Line 140: MUX_UPD(TOP_CAMTG2_SEL, clk_cfg_5, clk_cfg_5_set, clk_cfg_5_clr, 0, 3, clk_cfg_update, 20),
line over 96 characters
Patch Set #1, Line 141: MUX_UPD(TOP_CAMTG3_SEL, clk_cfg_5, clk_cfg_5_set, clk_cfg_5_clr, 8, 3, clk_cfg_update, 21),
line over 96 characters
Patch Set #1, Line 142: MUX_UPD(TOP_CAMTG4_SEL, clk_cfg_5, clk_cfg_5_set, clk_cfg_5_clr, 16, 3, clk_cfg_update, 22),
line over 96 characters
Patch Set #1, Line 143: MUX_UPD(TOP_CAMTG5_SEL, clk_cfg_5, clk_cfg_5_set, clk_cfg_5_clr, 24, 3, clk_cfg_update, 23),
line over 96 characters
Patch Set #1, Line 145: MUX_UPD(TOP_CAMTG6_SEL, clk_cfg_6, clk_cfg_6_set, clk_cfg_6_clr, 0, 3, clk_cfg_update, 24),
line over 96 characters
Patch Set #1, Line 146: MUX_UPD(TOP_UART_SEL, clk_cfg_6, clk_cfg_6_set, clk_cfg_6_clr, 8, 1, clk_cfg_update, 25),
line over 96 characters
Patch Set #1, Line 147: MUX_UPD(TOP_SPI_SEL, clk_cfg_6, clk_cfg_6_set, clk_cfg_6_clr, 16, 2, clk_cfg_update, 26),
line over 96 characters
Patch Set #1, Line 148: MUX_UPD(TOP_MSDC50_0_HCLK_SEL, clk_cfg_6, clk_cfg_6_set, clk_cfg_6_clr, 24, 2, clk_cfg_update, 27),
line over 96 characters
Patch Set #1, Line 150: MUX_UPD(TOP_MSDC50_0_SEL, clk_cfg_7, clk_cfg_7_set, clk_cfg_7_clr, 0, 3, clk_cfg_update, 28),
line over 96 characters
Patch Set #1, Line 151: MUX_UPD(TOP_MSDC30_1_SEL, clk_cfg_7, clk_cfg_7_set, clk_cfg_7_clr, 8, 3, clk_cfg_update, 29),
line over 96 characters
Patch Set #1, Line 152: MUX_UPD(TOP_MSDC30_2_SEL, clk_cfg_7, clk_cfg_7_set, clk_cfg_7_clr, 16, 3, clk_cfg_update, 30),
line over 96 characters
Patch Set #1, Line 153: MUX_UPD(TOP_AUDIO_SEL, clk_cfg_7, clk_cfg_7_set, clk_cfg_7_clr, 24, 2, clk_cfg_update1, 0),
line over 96 characters
Patch Set #1, Line 155: MUX_UPD(TOP_AUD_INTBUS_SEL, clk_cfg_8, clk_cfg_8_set, clk_cfg_8_clr, 0, 2, clk_cfg_update1, 1),
line over 96 characters
Patch Set #1, Line 156: MUX_UPD(TOP_PWRAP_ULPOSC_SEL, clk_cfg_8, clk_cfg_8_set, clk_cfg_8_clr, 8, 3, clk_cfg_update1, 2),
line over 96 characters
Patch Set #1, Line 157: MUX_UPD(TOP_ATB_SEL, clk_cfg_8, clk_cfg_8_set, clk_cfg_8_clr, 16, 2, clk_cfg_update1, 3),
line over 96 characters
Patch Set #1, Line 158: MUX_UPD(TOP_PWRMCU_SEL, clk_cfg_8, clk_cfg_8_set, clk_cfg_8_clr, 24, 3, clk_cfg_update1, 4),
line over 96 characters
Patch Set #1, Line 161: MUX_UPD(TOP_SCAM_SEL, clk_cfg_9, clk_cfg_9_set, clk_cfg_9_clr, 8, 1, clk_cfg_update1, 6),
line over 96 characters
Patch Set #1, Line 162: MUX_UPD(TOP_DISP_PWM_SEL, clk_cfg_9, clk_cfg_9_set, clk_cfg_9_clr, 16, 3, clk_cfg_update1, 7),
line over 96 characters
Patch Set #1, Line 163: MUX_UPD(TOP_USB_TOP_SEL, clk_cfg_9, clk_cfg_9_set, clk_cfg_9_clr, 24, 2, clk_cfg_update1, 8),
line over 96 characters
Patch Set #1, Line 165: MUX_UPD(TOP_SSUSB_XHCI_SEL, clk_cfg_10, clk_cfg_10_set, clk_cfg_10_clr, 0, 2, clk_cfg_update1, 9),
line over 96 characters
Patch Set #1, Line 166: MUX_UPD(TOP_I2C_SEL, clk_cfg_10, clk_cfg_10_set, clk_cfg_10_clr, 8, 2, clk_cfg_update1, 10),
line over 96 characters
Patch Set #1, Line 167: MUX_UPD(TOP_SENINF_SEL, clk_cfg_10, clk_cfg_10_set, clk_cfg_10_clr, 16, 3, clk_cfg_update1, 11),
line over 96 characters
Patch Set #1, Line 168: MUX_UPD(TOP_SENINF1_SEL, clk_cfg_10, clk_cfg_10_set, clk_cfg_10_clr, 24, 3, clk_cfg_update1, 12),
line over 96 characters
Patch Set #1, Line 170: MUX_UPD(TOP_SENINF2_SEL, clk_cfg_11, clk_cfg_11_set, clk_cfg_11_clr, 0, 3, clk_cfg_update1, 13),
line over 96 characters
Patch Set #1, Line 171: MUX_UPD(TOP_SENINF3_SEL, clk_cfg_11, clk_cfg_11_set, clk_cfg_11_clr, 8, 3, clk_cfg_update1, 14),
line over 96 characters
Patch Set #1, Line 172: MUX_UPD(TOP_TL_SEL, clk_cfg_11, clk_cfg_11_set, clk_cfg_11_clr, 16, 2, clk_cfg_update1, 15),
line over 96 characters
Patch Set #1, Line 173: MUX_UPD(TOP_DXCC_SEL, clk_cfg_11, clk_cfg_11_set, clk_cfg_11_clr, 24, 2, clk_cfg_update1, 16),
line over 96 characters
Patch Set #1, Line 175: MUX_UPD(TOP_AUD_ENGEN1_SEL, clk_cfg_12, clk_cfg_12_set, clk_cfg_12_clr, 0, 2, clk_cfg_update1, 17),
line over 96 characters
Patch Set #1, Line 176: MUX_UPD(TOP_AUD_ENGEN2_SEL, clk_cfg_12, clk_cfg_12_set, clk_cfg_12_clr, 8, 2, clk_cfg_update1, 18),
line over 96 characters
Patch Set #1, Line 177: MUX_UPD(TOP_AES_UFSFDE_SEL, clk_cfg_12, clk_cfg_12_set, clk_cfg_12_clr, 16, 3, clk_cfg_update1, 19),
line over 96 characters
Patch Set #1, Line 178: MUX_UPD(TOP_UFS_SEL, clk_cfg_12, clk_cfg_12_set, clk_cfg_12_clr, 24, 3, clk_cfg_update1, 20),
line over 96 characters
Patch Set #1, Line 180: MUX_UPD(TOP_AUD_1_SEL, clk_cfg_13, clk_cfg_13_set, clk_cfg_13_clr, 0, 1, clk_cfg_update1, 21),
line over 96 characters
Patch Set #1, Line 181: MUX_UPD(TOP_AUD_2_SEL, clk_cfg_13, clk_cfg_13_set, clk_cfg_13_clr, 8, 1, clk_cfg_update1, 22),
line over 96 characters
Patch Set #1, Line 182: MUX_UPD(TOP_ADSP_SEL, clk_cfg_13, clk_cfg_13_set, clk_cfg_13_clr, 16, 3, clk_cfg_update1, 23),
line over 96 characters
Patch Set #1, Line 183: MUX_UPD(TOP_DPMAIF_MAIN_SEL, clk_cfg_13, clk_cfg_13_set, clk_cfg_13_clr, 24, 3, clk_cfg_update1, 24),
line over 96 characters
Patch Set #1, Line 185: MUX_UPD(TOP_VENC_SEL, clk_cfg_14, clk_cfg_14_set, clk_cfg_14_clr, 0, 4, clk_cfg_update1, 25),
line over 96 characters
Patch Set #1, Line 186: MUX_UPD(TOP_VDEC_SEL, clk_cfg_14, clk_cfg_14_set, clk_cfg_14_clr, 8, 4, clk_cfg_update1, 26),
line over 96 characters
Patch Set #1, Line 187: MUX_UPD(TOP_CAMTM_SEL, clk_cfg_14, clk_cfg_14_set, clk_cfg_14_clr, 16, 2, clk_cfg_update1, 27),
line over 96 characters
Patch Set #1, Line 188: MUX_UPD(TOP_PWM_SEL, clk_cfg_14, clk_cfg_14_set, clk_cfg_14_clr, 24, 1, clk_cfg_update1, 28),
line over 96 characters
Patch Set #1, Line 190: MUX_UPD(TOP_AUDIO_H_SEL, clk_cfg_15, clk_cfg_15_set, clk_cfg_15_clr, 0, 2, clk_cfg_update1, 29),
line over 96 characters
Patch Set #1, Line 191: MUX_UPD(TOP_SPMI_MST_SEL, clk_cfg_15, clk_cfg_15_set, clk_cfg_15_clr, 8, 3, clk_cfg_update1, 30),
line over 96 characters
Patch Set #1, Line 192: MUX_UPD(TOP_DVFSRC_SEL, clk_cfg_15, clk_cfg_15_set, clk_cfg_15_clr, 16, 1, clk_cfg_update2, 0),
line over 96 characters
Patch Set #1, Line 193: MUX_UPD(TOP_AES_MSDCFDE_SEL, clk_cfg_15, clk_cfg_15_set, clk_cfg_15_clr, 24, 3, clk_cfg_update2, 1),
line over 96 characters
Patch Set #1, Line 195: MUX_UPD(TOP_MCUPM_SEL, clk_cfg_16, clk_cfg_16_set, clk_cfg_16_clr, 0, 2, clk_cfg_update2, 2),
line over 96 characters
Patch Set #1, Line 196: MUX_UPD(TOP_SFLASH_SEL, clk_cfg_16, clk_cfg_16_set, clk_cfg_16_clr, 8, 2, clk_cfg_update2, 3),
line over 96 characters
Patch Set #1, Line 457: setbits32(&mtk_topckgen->clk_scp_cfg_0 , 0x3ff);
space prohibited before that ',' (ctx:WxW)
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