Shaunak Saha has uploaded this change for review.
TGL: Make the GPIO asl table in sync with kernel
Kernel pinctrl driver changed for Tiger lake and went to old scheme.
Kernel patch: https://chromium-review.googlesource.com/c/chromiumos/
third_party/kernel/+/2116670
BRANCH=none
TEST=Build and boot tgl board. In /sys/kernel/debug/pinctrl
verify INTC34C5:00 listing all the pins.
Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
---
M src/mainboard/google/volteer/variants/baseboard/gpio.c
M src/mainboard/google/volteer/variants/ripto/gpio.c
M src/soc/intel/tigerlake/acpi/gpio.asl
M src/soc/intel/tigerlake/include/soc/gpio.h
4 files changed, 149 insertions(+), 101 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/39801/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c
index fff0381..b332856 100644
--- a/src/mainboard/google/volteer/variants/baseboard/gpio.c
+++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c
@@ -459,8 +459,8 @@
}
static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM1_NAME),
- CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM1_NAME),
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
};
const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
diff --git a/src/mainboard/google/volteer/variants/ripto/gpio.c b/src/mainboard/google/volteer/variants/ripto/gpio.c
index 4159cb8..290aa3b 100644
--- a/src/mainboard/google/volteer/variants/ripto/gpio.c
+++ b/src/mainboard/google/volteer/variants/ripto/gpio.c
@@ -455,8 +455,8 @@
}
static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
- CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME),
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
};
const struct cros_gpio *variant_cros_gpios(size_t *num)
diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl
index 9bf0c60..344a096 100644
--- a/src/soc/intel/tigerlake/acpi/gpio.asl
+++ b/src/soc/intel/tigerlake/acpi/gpio.asl
@@ -17,101 +17,153 @@
#include <intelblocks/gpio.h>
#include "gpio_op.asl"
-Device (GCM0)
-{
- Name (_HID, CROS_GPIO_NAME)
- Name (_UID, 0)
- Name (_DDN, "GPIO Controller Community 0")
-
- Name (RBUF, ResourceTemplate()
+#if CONFIG(SOC_INTEL_TIGERLAKE)
+ Device (GPIO)
{
- Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ Name (_HID, "INT34C5")
+ Name (_UID, 0)
+ Name (_DDN, "GPIO Controller")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, 0, COM0)
+ Memory32Fixed (ReadWrite, 0, 0, COM1)
+ Memory32Fixed (ReadWrite, 0, 0, COM4)
+ Memory32Fixed (ReadWrite, 0, 0, COM5)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ /* GPIO Community 0 */
+ CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
+ CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
+ BAS0 = ^^PCRB (PID_GPIOCOM0)
+ LEN0 = GPIO_BASE_SIZE
+
+ /* GPIO Community 1 */
+ CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+ CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
+ BAS1 = ^^PCRB (PID_GPIOCOM1)
+ LEN1 = GPIO_BASE_SIZE
+
+ /* GPIO Community 4 */
+ CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
+ CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
+ BAS4 = ^^PCRB (PID_GPIOCOM4)
+ LEN4 = GPIO_BASE_SIZE
+
+ /* GPIO Community 5 */
+ CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
+ CreateDWordField (^RBUF, ^COM5._LEN, LEN5)
+ BAS5 = ^^PCRB (PID_GPIOCOM5)
+ LEN5 = GPIO_BASE_SIZE
+
+ Return (RBUF)
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0xF)
+ }
+ }
+#else
+ Device (GCM0)
+ {
+ Name (_HID, CROS_GPIO_NAME)
+ Name (_UID, 0)
+ Name (_DDN, "GPIO Controller Community 0")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
+ BAS0 = ^^PCRB (PID_GPIOCOM0)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+ }
+
+ Device (GCM1)
+ {
+ Name (_HID, CROS_GPIO_NAME)
+ Name (_UID, 1)
+ Name (_DDN, "GPIO Controller Community 1")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+ BAS1 = ^^PCRB (PID_GPIOCOM1)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+ }
+
+ Device (GCM4)
+ {
+ Name (_HID, CROS_GPIO_NAME)
+ Name (_UID, 4)
+ Name (_DDN, "GPIO Controller Community 4")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
+ BAS4 = ^^PCRB (PID_GPIOCOM4)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+ }
+
+ Device (GCM5)
+ {
+ Name (_HID, CROS_GPIO_NAME)
+ Name (_UID, 5)
+ Name (_DDN, "GPIO Controller Community 5")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
{ GPIO_IRQ14 }
- })
- Method (_CRS, 0, NotSerialized)
- {
- CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
- BAS0 = ^^PCRB (PID_GPIOCOM0)
- Return (^RBUF)
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
+ BAS5 = ^^PCRB (PID_GPIOCOM5)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
}
- Method (_STA)
- {
- Return (0xF)
- }
-}
-
-Device (GCM1)
-{
- Name (_HID, CROS_GPIO_NAME)
- Name (_UID, 1)
- Name (_DDN, "GPIO Controller Community 1")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
- { GPIO_IRQ14 }
- })
- Method (_CRS, 0, NotSerialized)
- {
- CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
- BAS1 = ^^PCRB (PID_GPIOCOM1)
- Return (^RBUF)
- }
- Method (_STA)
- {
- Return (0xF)
- }
-}
-
-Device (GCM4)
-{
- Name (_HID, CROS_GPIO_NAME)
- Name (_UID, 4)
- Name (_DDN, "GPIO Controller Community 4")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
- { GPIO_IRQ14 }
- })
- Method (_CRS, 0, NotSerialized)
- {
- CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
- BAS4 = ^^PCRB (PID_GPIOCOM4)
- Return (^RBUF)
- }
- Method (_STA)
- {
- Return (0xF)
- }
-}
-
-Device (GCM5)
-{
- Name (_HID, CROS_GPIO_NAME)
- Name (_UID, 5)
- Name (_DDN, "GPIO Controller Community 5")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
- { GPIO_IRQ14 }
- })
- Method (_CRS, 0, NotSerialized)
- {
- CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
- BAS5 = ^^PCRB (PID_GPIOCOM5)
- Return (^RBUF)
- }
- Method (_STA)
- {
- Return (0xF)
- }
-}
+#endif
/*
* Get GPIO DW0 Address
diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h
index 7a6df7c..dee59a3 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio.h
@@ -20,11 +20,7 @@
#if CONFIG(SOC_INTEL_TIGERLAKE)
- #define CROS_GPIO_NAME "INT34C5"
- #define CROS_GPIO_COMM0_NAME "INT34C5:00"
- #define CROS_GPIO_COMM1_NAME "INT34C5:01"
- #define CROS_GPIO_COMM4_NAME "INT34C5:02"
- #define CROS_GPIO_COMM5_NAME "INT34C5:03"
+ #define CROS_GPIO_DEVICE_NAME "INT34C5:00"
#elif CONFIG(SOC_INTEL_JASPERLAKE)
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