Angel Pons has uploaded this change for review.
haswell: Factor out `max_ddr3_freq`
All mainboards choose the maximum speed of DDR3-1600.
Change-Id: I8863f9d1df950b924f596689ebf1bfda5d317e06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/mainboard/asrock/b85m_pro4/romstage.c
M src/mainboard/asrock/h81m-hds/romstage.c
M src/mainboard/google/beltino/romstage.c
M src/mainboard/google/slippy/romstage.c
M src/mainboard/intel/baskingridge/romstage.c
M src/mainboard/lenovo/t440p/romstage.c
M src/mainboard/supermicro/x10slm-f/romstage.c
M src/northbridge/intel/haswell/romstage.c
8 files changed, 1 insertion(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/43120/1
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c
index c9dd8d4..c9eb981 100644
--- a/src/mainboard/asrock/b85m_pro4/romstage.c
+++ b/src/mainboard/asrock/b85m_pro4/romstage.c
@@ -29,7 +29,6 @@
pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0;
pei_data->gbe_enable = 1;
- pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index febaa63..f29bd70 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -26,7 +26,6 @@
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[2] = 0xa4;
pei_data->ec_present = 0;
- pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index fe3275e..525edf4 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -51,7 +51,6 @@
/* Enable 2x refresh mode */
pei_data->ddr_refresh_2x = 1;
pei_data->dq_pins_interleaved = 1;
- pei_data->max_ddr3_freq = 1600;
pei_data->usb_xhci_on_resume = 1;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index ea95853..6145432 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -48,7 +48,6 @@
pei_data->spd_addresses[0] = 0xff;
pei_data->spd_addresses[2] = 0xff;
pei_data->ec_present = 1;
- pei_data->max_ddr3_freq = 1600;
pei_data->usb_xhci_on_resume = 1;
variant_romstage_entry(pei_data);
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index a156095..6b2dfa7 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -52,7 +52,6 @@
pei_data->spd_addresses[2] = 0xa4;
pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0;
- pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c
index e101794..7b09df4 100644
--- a/src/mainboard/lenovo/t440p/romstage.c
+++ b/src/mainboard/lenovo/t440p/romstage.c
@@ -49,7 +49,6 @@
pei_data->spd_addresses[2] = 0xa2;
pei_data->ec_present = 1;
pei_data->gbe_enable = 1;
- pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index 1606d5f..64d6981 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -28,7 +28,6 @@
pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0;
pei_data->ddr_refresh_2x = 1;
- pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 6231452..59e3c32 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -52,6 +52,7 @@
.gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000,
.tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .max_ddr3_freq = 1600,
};
mainboard_fill_pei_data(&pei_data);
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