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soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing

- Enable Trace Hub
- Set debugger mode to Host debugger

Branch=None
Test=Build and boot on ADL-M RVP. Execute BVT TAST test cases

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I16086e3ce92c5d54fbeae9444c0608b31c1ad01e
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/soc/intel/alderlake/romstage/fsp_params.c
3 files changed, 28 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/52140/1

diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index c1c4586..8169f3b 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -18,6 +18,7 @@
 	select HAVE_SPD_IN_CBFS
 	select DRIVERS_SOUNDWIRE_ALC711
 	select SOC_INTEL_CSE_LITE_SKU
+	select SOC_INTEL_DEBUG_CONSENT
 
 config CHROMEOS
 	select GBB_FLAG_FORCE_DEV_SWITCH_ON
@@ -61,6 +62,22 @@
 	string
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
+config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT
+	int "Debug Consent for ADL"
+	# USB DBC is more common for developers so make this default to 3 if
+	# SOC_INTEL_DEBUG_CONSENT=y
+	default 7 if SOC_INTEL_DEBUG_CONSENT
+	default 0
+	help
+	  This is to control debug interface on SOC.
+	  Setting non-zero value will allow to use DBC or DCI to debug SOC.
+	  PlatformDebugConsent in FspmUpd.h has the details.
+
+	  Desired platform debug type are
+	  0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
+	  3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
+	  6:Enable (2-wire DCI OOB), 7:Manual
+
 config DIMM_SPD_SIZE
 	int
 	default 512
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 7c69163..2995670 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -260,6 +260,6 @@
 		device pci 1f.4 on  end # SMBus
 		device pci 1f.5 on  end # SPI
 		device pci 1f.6 off end # GbE
-		device pci 1f.7 off end # TH
+		device pci 1f.7 on end # TH
 	end
 end
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 3852467..04ccf94 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -126,6 +126,16 @@
 	/* Set debug probe type */
 	m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;
 
+	/* Disable DCI DBC mode */
+	m_cfg->DciDbcMode = 0;
+
+	/* Disable platform debugger support */
+	m_cfg->DciUsb3TypecUfpDbg = 0;
+
+	/* Set trace debug mode to Host Debugger Mode */
+	m_cfg->PchTraceHubMode = 2;
+	m_cfg->CpuTraceHubMode = 2;
+
 	/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
 	dev = pcidev_path_on_root(PCH_DEVFN_HDA);
 	m_cfg->PchHdaEnable = is_dev_enabled(dev);

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