Marshall Dawson uploaded patch set #5 to this change.

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soc/amd/stoneyridge: Rework SPI base address get/set

A subsequent patch will move the soc//stoneyridge LPC functionality to
a common directory.  Prepare by reworking the SPI BAR configuration
function in southbridge.h.  The SPI BAR is not a typical PCI BAR, and
is at D14F3xA0.

Change-Id: I73ddb4afaf9e67ca0522ecb6085b23c92fedc461
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/lpc.c
M src/soc/amd/stoneyridge/southbridge.c
3 files changed, 41 insertions(+), 20 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32652/5

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