Morgan Jang has uploaded this change for review.
rc/soc/intel/fsp_broadwell_de/acpi: Support Linux GPIO driver for Monolake platform
TEST=Test with the Linux Kernel that enables GPIO sysfs interface,
Intel ICH GPIO and Intel Lynxpoint GPIO support in kernel config.
Change-Id: I6387faed4dc97c9efc130aa3ade4754118edc8b8
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
---
M src/soc/intel/fsp_broadwell_de/acpi.c
A src/soc/intel/fsp_broadwell_de/acpi/gpio.asl
M src/soc/intel/fsp_broadwell_de/acpi/lpc.asl
3 files changed, 162 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37545/1
diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c
index 5349c30..0ba9159 100644
--- a/src/soc/intel/fsp_broadwell_de/acpi.c
+++ b/src/soc/intel/fsp_broadwell_de/acpi.c
@@ -117,7 +117,7 @@
unsigned long acpi_fill_mcfg(unsigned long current)
{
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
- MCFG_BASE_ADDRESS, 0, 0, 255);
+ MCFG_BASE_ADDRESS, 0, 0, 255);
return current;
}
@@ -532,7 +532,7 @@
irqovr = (void *)current;
current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq,
- sci_flags);
+ sci_flags);
return current;
}
diff --git a/src/soc/intel/fsp_broadwell_de/acpi/gpio.asl b/src/soc/intel/fsp_broadwell_de/acpi/gpio.asl
new file mode 100644
index 0000000..d1132d4
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/acpi/gpio.asl
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (GPIO)
+{
+ // GPIO Controller
+ Method (_HID)
+ {
+ // LynxPoint-LP
+ Return ("INT33C7")
+ }
+ Name (_UID, 1)
+
+ Name (RBUF, ResourceTemplate()
+ {
+ DWordIo (ResourceProducer,
+ MinFixed, // IsMinFixed
+ MaxFixed, // IsMaxFixed
+ PosDecode, // Decode
+ EntireRange, // ISARanges
+ 0x00000000, // AddressGranularity
+ 0x00000000, // AddressMinimum
+ 0x00000000, // AddressMaximum
+ 0x00000000, // AddressTranslation
+ 0x00000000, // RangeLength
+ , // ResourceSourceIndex
+ , // ResourceSource
+ BAR0)
+ // Disabled due to IRQ storm: http://crosbug.com/p/29548
+ //Interrupt (ResourceConsumer,
+ // Level, ActiveHigh, Shared, , , ) {14}
+ })
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^BAR0._MIN, BMIN)
+ CreateDwordField (^RBUF, ^BAR0._MAX, BMAX)
+ CreateDwordField (^RBUF, ^BAR0._LEN, BLEN)
+
+ Store (GPIO_BASE_SIZE, BLEN)
+ Store (GPIO_BASE_ADDRESS, BMIN)
+ Store (Subtract (Add (GPIO_BASE_ADDRESS,
+ GPIO_BASE_SIZE), 1), BMAX)
+
+ Return (RBUF)
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0xF)
+ }
+
+ // GWAK: Setup GPIO as ACPI GPE for Wake
+ // Arg0: GPIO Number
+ Method (GWAK, 1, Serialized)
+ {
+ // Local0 = GPIO Base Address
+ Store (And (GPBS, Not(0x1)), Local0)
+
+ // Local1 = BANK, Local2 = OFFSET
+ Divide (Arg0, 32, Local2, Local1)
+
+ //
+ // Set OWNER to ACPI
+ //
+
+ // Local3 = GPIOBASE + GPIO_OWN(BANK)
+ Store (Add (Local0, Multiply (Local1, 0x4)), Local3)
+
+ // GPIO_OWN(BANK)
+ OperationRegion (IOWN, SystemIO, Local3, 4)
+ Field (IOWN, AnyAcc, NoLock, Preserve) {
+ GOWN, 32,
+ }
+
+ // GPIO_OWN[GPIO] = 0 (ACPI)
+ Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN)
+
+ //
+ // Set ROUTE to SCI
+ //
+
+ // Local3 = GPIOBASE + GPIO_ROUTE(BANK)
+ Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3)
+
+ // GPIO_ROUTE(BANK)
+ OperationRegion (IROU, SystemIO, Local3, 4)
+ Field (IROU, AnyAcc, NoLock, Preserve) {
+ GROU, 32,
+ }
+
+ // GPIO_ROUTE[GPIO] = 0 (SCI)
+ Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU)
+
+ //
+ // Set GPnCONFIG to GPIO|INPUT|INVERT
+ //
+
+ // Local3 = GPIOBASE + GPnCONFIG0(GPIO)
+ Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3)
+
+ // GPnCONFIG(GPIO)
+ OperationRegion (GPNC, SystemIO, Local3, 8)
+ Field (GPNC, AnyAcc, NoLock, Preserve) {
+ GMOD, 1, // MODE: 0=NATIVE 1=GPIO
+ , 1,
+ GIOS, 1, // IO_SEL: 0=OUTPUT 1=INPUT
+ GINV, 1, // INVERT: 0=NORMAL 1=INVERT
+ GLES, 1, // LxEB: 0=EDGE 1=LEVEL
+ , 24,
+ ILVL, 1, // INPUT: 0=LOW 1=HIGH
+ OLVL, 1, // OUTPUT: 0=LOW 1=HIGH
+ GPWP, 2, // PULLUP: 00=NONE 01=DOWN 10=UP 11=INVALID
+ ISEN, 1, // SENSE: 0=ENABLE 1=DISABLE
+ }
+
+ Store (0x1, GMOD) // GPIO
+ Store (0x1, GIOS) // INPUT
+ Store (0x1, GINV) // INVERT
+ }
+}
diff --git a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl
index ef1e655..24da73e 100644
--- a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl
+++ b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl
@@ -23,6 +23,31 @@
#include "irqlinks.asl"
+ OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
+ Field (LPC0, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x02),
+ PDID, 16, // Device ID
+ Offset (0x40),
+ PMBS, 16, // PMBASE
+ Offset (0x48),
+ GPBS, 16, // GPIOBASE
+ Offset (0x60), // Interrupt Routing Registers
+ PRTA, 8,
+ PRTB, 8,
+ PRTC, 8,
+ PRTD, 8,
+ Offset (0x68),
+ PRTE, 8,
+ PRTF, 8,
+ PRTG, 8,
+ PRTH, 8,
+
+ Offset (0x80), // IO Decode Ranges
+ IOD0, 8,
+ IOD1, 8,
+ }
+
Device (FWH) // Firmware Hub
{
Name (_HID, EISAID("INT0800"))
@@ -89,4 +114,6 @@
IRQNoFlags() {0}
})
}
+
+ #include "gpio.asl"
}
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