Johnny Lin has uploaded this change for review.

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mb/ocp/deltalake: Configure IIO PCIe ports via FSP

Change-Id: I7cff6d71588f91c3210cbaa17484644d5b89cc62
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
---
M src/mainboard/ocp/deltalake/cpxsp_dl_iio.h
M src/mainboard/ocp/deltalake/romstage.c
M src/soc/intel/xeon_sp/cpx/acpi.c
M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
5 files changed, 271 insertions(+), 80 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/42096/1
diff --git a/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h b/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h
index b7f8c85..b9535ff 100644
--- a/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h
+++ b/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h
@@ -5,69 +5,82 @@

#include <FspmUpd.h>
#include <soc/pci_devs.h>
+#include <hob_iiouds.h>

-#if 0
/*
* DeltaLake Iio PCIe Port Table
*/
-static const UPD_PCI_PORT_CONFIG dl_iio_pci_port = {
- // PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload |
- // DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd |
- // NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 |
- // NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 |
- // NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride
-/*
- { PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_2C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_2D, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_3A, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_4A, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_4B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_4C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
- { PORT_4D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
- 0x16, 0x00, 0x03 },
-*/
+static const UPD_IIO_PCIE_PORT_CONFIG dl_iio_pci_port[] = {
+ /* Socket | PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload |
+ DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbIndex |
+ NtbPpd | NtbBarSizeOverride | NtbSplitBar | NtbBarSizeImBar1 | NtbBarSizeImBar2
+ NtbBarSizeImBar2_0 | NtbBarSizeImBar2_1| NtbBarSizeEmBarSZ1 | NtbBarSizeEmBarSZ2
+ NtbBarSizeEmBarSZ2_0 | NtbBarSizeEmBarSZ2_1 | NtbXlinkCtlOverride */
+ /* PORT_1A ~ PORT_1D */
+ { 0, PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0,
+ 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF,
+ NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16,
+ 0x0C, 0x0C, 0x16, 0x16,
+ 0x0C, 0x0C, 0x03},
+ { 0, PORT_1B, NOT_HIDE, 0x00, PcieAuto, 0x0,
+ 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF,
+ NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16,
+ 0x0C, 0x0C, 0x16, 0x16,
+ 0x0C, 0x0C, 0x03},
+ { 0, PORT_1C, NOT_HIDE, 0x00, PcieAuto, 0x0,
+ 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF,
+ NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16,
+ 0x0C, 0x0C, 0x16, 0x16,
+ 0x0C, 0x0C, 0x03},
+ { 0, PORT_1D, NOT_HIDE, 0x00, PcieAuto, 0x0,
+ 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF,
+ NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16,
+ 0x0C, 0x0C, 0x16, 0x16,
+ 0x0C, 0x0C, 0x03},
+ /* PORT_2A ~ PORT_2D */
+ { 0, PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0,
+ 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF,
+ NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16,
+ 0x0C, 0x0C, 0x16, 0x16,
+ 0x0C, 0x0C, 0x03},
+ { 0, PORT_2B, NOT_HIDE, 0x00, PcieAuto, 0x0,
+ 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF,
+ NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16,
+ 0x0C, 0x0C, 0x16, 0x16,
+ 0x0C, 0x0C, 0x03},
+ { 0, PORT_2C, NOT_HIDE, 0x00, PcieAuto, 0x0,
+ 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF,
+ NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16,
+ 0x0C, 0x0C, 0x16, 0x16,
+ 0x0C, 0x0C, 0x03},
+ { 0, PORT_2D, NOT_HIDE, 0x00, PcieAuto, 0x0,
+ 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF,
+ NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16,
+ 0x0C, 0x0C, 0x16, 0x16,
+ 0x0C, 0x0C, 0x03},
+ /* PORT_3A ~ PORT_3D does not exist */
+ /* PORT_4A ~ PORT_4D */
+ { 0, PORT_4A, NOT_HIDE, 0x00, PcieAuto, 0x0,
+ 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF,
+ NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16,
+ 0x0C, 0x0C, 0x16, 0x16,
+ 0x0C, 0x0C, 0x03},
+ { 0, PORT_4B, NOT_HIDE, 0x00, PcieAuto, 0x0,
+ 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF,
+ NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16,
+ 0x0C, 0x0C, 0x16, 0x16,
+ 0x0C, 0x0C, 0x03},
+ { 0, PORT_4C, NOT_HIDE, 0x00, PcieAuto, 0x0,
+ 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF,
+ NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16,
+ 0x0C, 0x0C, 0x16, 0x16,
+ 0x0C, 0x0C, 0x03},
+ { 0, PORT_4D, NOT_HIDE, 0x00, PcieAuto, 0x0,
+ 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF,
+ NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16,
+ 0x0C, 0x0C, 0x16, 0x16,
+ 0x0C, 0x0C, 0x03},
};
-#endif

/*
* DeltaLake PCH PCIe Port Table
diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c
index eabbd6b..ecfb910 100644
--- a/src/mainboard/ocp/deltalake/romstage.c
+++ b/src/mainboard/ocp/deltalake/romstage.c
@@ -61,13 +61,30 @@
uint8_t index;

oem_update_iio(mupd);
-
-#if 0
- mupd->FspmConfig.IioPciConfig.ConfigurationTable =
- (UPD_PCI_PORT_CONFIG *) dl_iio_pci_port;
- mupd->FspmConfig.IioPciConfig.NumberOfEntries =
- ARRAY_SIZE(dl_iio_pci_port);
-#endif
+ /* Config IIO PCIe ports from table */
+ mupd->FspmConfig.IioPcieConfigTablePtr = (uint32_t) dl_iio_pci_port;
+ mupd->FspmConfig.IioPcieConfigTableNumber = ARRAY_SIZE(dl_iio_pci_port);
+ /* Config all IIO PCIe ports? */
+ mupd->FspmConfig.IIOPcieRootPortEnable = 1;
+ mupd->FspmConfig.DeEmphasis = 0x00;
+ mupd->FspmConfig.IIOPciePortLinkSpeed = PcieAuto; //0
+ mupd->FspmConfig.IIOPcieMaxPayload = 0x0;
+ mupd->FspmConfig.DfxDnTxPreset = 0xFF;
+ mupd->FspmConfig.DfxRxPreset = 0xFF;
+ mupd->FspmConfig.DfxUpTxPreset = 0xFF;
+ mupd->FspmConfig.PcieCommonClock = 0x1;
+ mupd->FspmConfig.NtbPpd = NTB_PORT_TRANSPARENT; //0
+ mupd->FspmConfig.NtbBarSizeOverride = 0x00;
+ mupd->FspmConfig.NtbSplitBar = 0x00;
+ mupd->FspmConfig.NtbBarSizeImBar1 = 0x16;
+ mupd->FspmConfig.NtbBarSizeImBar2 = 0x16;
+ mupd->FspmConfig.NtbBarSizeImBar2_0 = 0x0C;
+ mupd->FspmConfig.NtbBarSizeImBar2_1 = 0x0C;
+ mupd->FspmConfig.NtbBarSizeEmBarSZ1 = 0x16;
+ mupd->FspmConfig.NtbBarSizeEmBarSZ2 = 0x16;
+ mupd->FspmConfig.NtbBarSizeEmBarSZ2_0 = 0x0C;
+ mupd->FspmConfig.NtbBarSizeEmBarSZ2_1 = 0x0C;
+ mupd->FspmConfig.NtbXlinkCtlOverride = 0x03;

for (index = 0; index < ARRAY_SIZE(dl_pch_pci_port); index++) {
mupd->FspmConfig.PchPcieForceEnable[dl_pch_pci_port[index].PortIndex] =
diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c
index 8cdd01e..6789e92 100644
--- a/src/soc/intel/xeon_sp/cpx/acpi.c
+++ b/src/soc/intel/xeon_sp/cpx/acpi.c
@@ -424,11 +424,11 @@
else if (p >= PORT_2A && p <= PORT_2D)
return PSTACK1;
else if (p >= PORT_4A && p <= PORT_4D)
- return PSTACK2;
+ return PSTACK3;
else if (p >= PORT_5A && p <= PORT_5D)
- return PSTACK3; // MCP0
+ return PSTACK4; // MCP0
else
- return PSTACK4; // MCP1
+ return MAX_STACKS; // MCP1
}

static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack,
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h
index 4374058..72a3b13 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h
@@ -77,6 +77,9 @@
KTI_LINK5
} KTI_LOGIC_LINK;

+#define HIDE 1
+#define NOT_HIDE 0
+
#define IIO_BIFURCATE_xxxxxxxx 0xFE
#define IIO_BIFURCATE_x4x4x4x4 0x0
#define IIO_BIFURCATE_x4x4xxx8 0x1
@@ -133,6 +136,44 @@
Iio_IouMax
} IIO_IOUS;

+typedef struct {
+ //For IioPcieConfig
+ UINT8 Socket;
+ UINT16 PortIndex;
+ UINT8 HidePort;
+ UINT8 DeEmphasis;
+ UINT8 PortLinkSpeed;
+ UINT8 MaxPayload;
+ UINT8 DfxDnTxPreset;
+ UINT8 DfxRxPreset;
+ UINT8 DfxUpTxPreset;
+ UINT8 Sris;
+ UINT8 PcieCommonClock;
+ //For IIO Ntb^M
+ UINT8 NtbIndex;
+ UINT8 NtbPpd;
+ UINT8 NtbBarSizeOverride;
+ UINT8 NtbSplitBar;
+ UINT8 NtbBarSizeImBar1;
+ UINT8 NtbBarSizeImBar2;
+ UINT8 NtbBarSizeImBar2_0;
+ UINT8 NtbBarSizeImBar2_1;
+ UINT8 NtbBarSizeEmBarSZ1;
+ UINT8 NtbBarSizeEmBarSZ2;
+ UINT8 NtbBarSizeEmBarSZ2_0;
+ UINT8 NtbBarSizeEmBarSZ2_1;
+ UINT8 NtbXlinkCtlOverride;
+} UPD_IIO_PCIE_PORT_CONFIG;
+
+/**
+ NTB Per Port Definition
+ **/
+typedef enum {
+ NTB_PORT_TRANSPARENT = 0,
+ NTB_PORT_NTB_NTB
+} NTB_PPD;
+
+
/**
UPD_PCH_PCIE_PORT:
PortIndex - PCH PCIe Port Index.
@@ -535,45 +576,160 @@
**/
UINT8 IioConfigIOU4[8];

-/** Offset 0x00F7 - PchAdrEn
+/** Offset 0x00F7
+**/
+ UINT8 UnusedUpdSpace4;
+
+/** Offset 0x00F8 - Usage type for IIO PCIE Config Table Ptr
+ IIO PCIE Config Table Ptr
+**/
+ UINT32 IioPcieConfigTablePtr;
+
+/** Offset 0x00FC - Usage type for IIO PCIE Config Table Number
+ IIO PCIE Config Table Number
+**/
+ UINT32 IioPcieConfigTableNumber;
+
+/** Offset 0x0100 - Usage type for IIO PCIE Root Port Enable or Disable
+ IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled,
+ the value is 0x00
+**/
+ UINT8 IIOPcieRootPortEnable;
+
+/** Offset 0x0101 - Usage type for IIO DeEmphasis
+ IIO DeEmphasis
+**/
+ UINT8 DeEmphasis;
+
+/** Offset 0x0102 - Usage type for IIO PCIE Root Port link speed
+ IIO root port link speed
+**/
+ UINT8 IIOPciePortLinkSpeed;
+
+/** Offset 0x0103 - Usage type for IIO PCIE Root Port Max Payload
+ IIO Root Port Max Payload
+**/
+ UINT8 IIOPcieMaxPayload;
+
+/** Offset 0x0104 - Usage type for IIO DfxDnTxPreset
+ IIO DfxDnTxPreset
+**/
+ UINT8 DfxDnTxPreset;
+
+/** Offset 0x0105 - Usage type for IIO DfxRxPreset
+ IIO DfxRxPreset
+**/
+ UINT8 DfxRxPreset;
+
+/** Offset 0x0106 - Usage type for IIO DfxUpTxPreset
+ IIO DfxUpTxPreset
+**/
+ UINT8 DfxUpTxPreset;
+
+/** Offset 0x0107 - Usage type for IIO PcieCommonClock
+ IIO PcieCommonClock
+**/
+ UINT8 PcieCommonClock;
+
+/** Offset 0x0108 - Usage type for IIO NtbPpd
+ IIO NtbPpd
+**/
+ UINT8 NtbPpd;
+
+/** Offset 0x0109 - Usage type for IIO NtbBarSizeOverride
+ IIO NtbBarSizeOverride
+**/
+ UINT8 NtbBarSizeOverride;
+
+/** Offset 0x010A - Usage type for IIO NtbSplitBar
+ IIO NtbSplitBar
+**/
+ UINT8 NtbSplitBar;
+
+/** Offset 0x010B - Usage type for IIO NtbBarSizeImBar1
+ IIO NtbBarSizeImBar1
+**/
+ UINT8 NtbBarSizeImBar1;
+
+/** Offset 0x010C - Usage type for IIO NtbBarSizeImBar2
+ IIO PNtbBarSizeImBar2
+**/
+ UINT8 NtbBarSizeImBar2;
+
+/** Offset 0x010D - Usage type for IIO NtbBarSizeImBar2_0
+ IIO PNtbBarSizeImBar2_0
+**/
+ UINT8 NtbBarSizeImBar2_0;
+
+/** Offset 0x010E - Usage type for IIO NtbBarSizeImBar2_1
+ IIO NtbBarSizeImBar2_1
+**/
+ UINT8 NtbBarSizeImBar2_1;
+
+/** Offset 0x010F - Usage type for IIO NtbBarSizeEmBarSZ1
+ IIO NtbBarSizeEmBarSZ1
+**/
+ UINT8 NtbBarSizeEmBarSZ1;
+
+/** Offset 0x0110 - Usage type for IIO NtbBarSizeEmBarSZ2
+ IIO NtbBarSizeEmBarSZ2
+**/
+ UINT8 NtbBarSizeEmBarSZ2;
+
+/** Offset 0x0111 - Usage type for IIO NtbBarSizeEmBarSZ2_0
+ IIO NtbBarSizeEmBarSZ2_0
+**/
+ UINT8 NtbBarSizeEmBarSZ2_0;
+
+/** Offset 0x0112 - Usage type for IIO NtbBarSizeEmBarSZ2_1
+ IIO NtbBarSizeEmBarSZ2_1
+**/
+ UINT8 NtbBarSizeEmBarSZ2_1;
+
+/** Offset 0x0113 - Usage type for IIO NtbXlinkCtlOverride
+ IIO NtbXlinkCtlOverride
+**/
+ UINT8 NtbXlinkCtlOverride;
+
+/** Offset 0x0114 - PchAdrEn
Enable or Disable PchAdr
**/
UINT8 PchAdrEn;

-/** Offset 0x00F8 - } TYPE:{Combo
+/** Offset 0x0115 - } TYPE:{Combo
Root port swapping based on device connection status : TRUE or FALSE
TRUE : 0x01, FALSE : 0x00
**/
UINT8 PchPcieRootPortFunctionSwap;

-/** Offset 0x00F9 - PCH PCIE PLL Ssc
+/** Offset 0x0116 - PCH PCIE PLL Ssc
Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC
of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF
**/
UINT8 PchPciePllSsc;

-/** Offset 0x00FA - Usage type for PCH PCIE Root Port Index
+/** Offset 0x0117 - Usage type for PCH PCIE Root Port Index
Index assigned to every PCH PCIE Root Port
**/
UINT8 PchPciePortIndex[20];

-/** Offset 0x010E - Usage type for PCH PCIE Root Port Enable or Disable
+/** Offset 0x012B - Usage type for PCH PCIE Root Port Enable or Disable
0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled,
the value is 0x00
**/
UINT8 PchPcieForceEnable[20];

-/** Offset 0x0122 - Usage type for PCH PCIE Root Port Link Speed
+/** Offset 0x013F - Usage type for PCH PCIE Root Port Link Speed
0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie
Gen2 Speed, 0x03 : Pcie Gen3 Speed
**/
UINT8 PchPciePortLinkSpeed[20];

-/** Offset 0x0136
+/** Offset 0x0153
**/
- UINT8 UnusedUpdSpace4[2];
+ UINT8 UnusedUpdSpace5[1];

-/** Offset 0x0138
+/** Offset 0x0154
**/
UINT8 ReservedMemoryInitUpd[16];
} FSP_M_CONFIG;
@@ -594,11 +750,11 @@
**/
FSP_M_CONFIG FspmConfig;

-/** Offset 0x0148
+/** Offset 0x0164
**/
- UINT8 UnusedUpdSpace5[6];
+ UINT8 UnusedUpdSpace6[2];

-/** Offset 0x014E
+/** Offset 0x0166
**/
UINT16 UpdTerminator;
} FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
index 7ac630f..79b7d7a 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
@@ -102,6 +102,11 @@
PORT_2C,
PORT_2D,
// IOU2
+ PORT_3A,
+ PORT_3B,
+ PORT_3C,
+ PORT_3D,
+ // IOU3
PORT_4A,
PORT_4B,
PORT_4C,

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Gerrit-Project: coreboot
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Gerrit-Change-Id: I7cff6d71588f91c3210cbaa17484644d5b89cc62
Gerrit-Change-Number: 42096
Gerrit-PatchSet: 1
Gerrit-Owner: Johnny Lin <Johnny_Lin@wiwynn.com>
Gerrit-MessageType: newchange