Patrick Rudolph submitted this change.

View Change

soc/intel/tigerlake: Add IRQs for LPSS uart

Values are taken from pci_irqs.asl.
The common code will make use of those defines to generate ACPI
SSDT code for LPSS uarts operating in "ACPI mode".

Change-Id: I5ef93493965834cda30d70918e65de3129e547b7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44260
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/soc/intel/tigerlake/include/soc/irq.h
1 file changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h
index ad70290..f95f9f6 100644
--- a/src/soc/intel/tigerlake/include/soc/irq.h
+++ b/src/soc/intel/tigerlake/include/soc/irq.h
@@ -9,4 +9,8 @@
 #define PCH_IRQ10	10
 #define PCH_IRQ11	11
 
+#define LPSS_UART0_IRQ	16
+#define LPSS_UART1_IRQ	17
+#define LPSS_UART2_IRQ	33
+
 #endif /* _SOC_IRQ_H_ */

To view, visit change 44260. To unsubscribe, or for help writing mail filters, visit settings.