Tristan Hsieh has uploaded this change for review.

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mediatek/mt8183: Add DDR driver of write leveling part

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
     patches.

Change-Id: Ibde5f613c61c36f5c9b405326fd18a3fd16cca56
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
---
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
1 file changed, 27 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/28840/1

diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
index 0542baa..7b42287 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
@@ -83,6 +83,31 @@
 	clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, mrs_back);
 }
 
+static void dramc_write_leveling(u8 chn, u8 rank,
+		const u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER])
+{
+	s32 clock_delay_max = 0;
+
+	dramc_show("chn:%d, rank:%d params write level:0x%x, 0x%x\n",
+		chn, rank, wr_level[chn][rank][0], wr_level[chn][rank][1]);
+
+	clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9],
+		SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK,
+		clock_delay_max << SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_SHIFT);
+
+	for (u8 i = 0; i < DQS_NUMBER; i++) {
+		s32 wrlevel_dq_delay = wr_level[chn][rank][i] + 0x10;
+		assert(wrlevel_dq_delay < 0x40);
+
+		clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[7],
+			FINE_TUNE_PBYTE_MASK | FINE_TUNE_DQM_MASK |
+			FINE_TUNE_DQ_MASK,
+			(wr_level[chn][rank][i] << FINE_TUNE_PBYTE_SHIFT) |
+			(wrlevel_dq_delay << FINE_TUNE_DQM_SHIFT) |
+			(wrlevel_dq_delay << FINE_TUNE_DQ_SHIFT));
+	}
+}
+
 static void cmd_bus_training(u8 chn, u8 rank,
 		const struct sdram_params *params)
 {
@@ -292,6 +317,8 @@
 			dramc_show("start K ch:%d, rank:%d\n", chn, rk);
 			auto_refresh_switch(chn, 0);
 			cmd_bus_training(chn, rk, pams);
+			dramc_write_leveling(chn, rk, pams->wr_level);
+			auto_refresh_switch(chn, 1);
 		}
 	}
 }

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