Benjamin Doron uploaded patch set #17 to this change.

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soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports

Port commit 84b4882b (soc/intel/tigerlake: Configure L1Substates for
PCH Root ports), CB:39412) to Skylake. Exposes PcieRpAspm and
PcieRpL1Substates to devicetree to allow boards to set these options.

get_{aspm,l1_substate}_control() ensure that the right UPD value is set in
fsp_params.

Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
2 files changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/17

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