Felix Singer submitted this change.
soc/intel/alderlake: Add Kconfigs for all PCH types
The Alder Lake code currently supports the PCH-M and PCH-P types, which
have some differences (so far, only the amount of PCIe I/O). Mainboards
can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which
PCH type they use: select the option to choose PCH-M, do not select the
option to choose PCH-P. While this works, it can be confusing once more
PCH types are added.
Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards
have to explicitly choose a PCH type. Also, use this option to restrict
the PCH-P defaults for PCH-dependent settings to avoid unintended reuse
of the PCH-P defaults when adding a new PCH type. To make sure only one
PCH type is selected, add some preprocessor in `bootblock.h` to provoke
a build-time error if this requirement is not met. Kconfig doesn't seem
to have a mechanism to describe sets of mutually-exclusive bool options
that allows said options to be selected (a `choice` block doesn't allow
its elements to be selected). Finally, adapt the ADL boards accordingly.
Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/shadowmountain/Kconfig
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/include/soc/bootblock.h
5 files changed, 26 insertions(+), 11 deletions(-)
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index a5ca942..4b25af5 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -45,7 +45,7 @@
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_I2C_TPM_CR50
select MAINBOARD_HAS_TPM2
- select SOC_INTEL_ALDERLAKE
+ select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
select SOC_INTEL_CSE_LITE_SKU
select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index 2b78515..6575685 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -14,7 +14,6 @@
select HAVE_ACPI_TABLES
select HAVE_SPD_IN_CBFS
select MAINBOARD_HAS_CHROMEOS
- select SOC_INTEL_ALDERLAKE
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
@@ -23,11 +22,13 @@
select BOARD_INTEL_ADLRVP_COMMON
select DRIVERS_UART_8250IO
select MAINBOARD_USES_IFD_EC_REGION
+ select SOC_INTEL_ALDERLAKE_PCH_P
config BOARD_INTEL_ADLRVP_P_EXT_EC
select BOARD_INTEL_ADLRVP_COMMON
select DRIVERS_INTEL_PMC
select INTEL_LPSS_UART_FOR_CONSOLE
+ select SOC_INTEL_ALDERLAKE_PCH_P
config BOARD_INTEL_ADLRVP_P_MCHP
select BOARD_INTEL_ADLRVP_COMMON
@@ -36,7 +37,7 @@
select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
select EC_GOOGLE_CHROMEEC_MEC
select INTEL_LPSS_UART_FOR_CONSOLE
- select SOC_INTEL_COMMON_BLOCK_IPU
+ select SOC_INTEL_ALDERLAKE_PCH_P
config BOARD_INTEL_ADLRVP_M
select BOARD_INTEL_ADLRVP_COMMON
diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig
index 553906a..9294857 100644
--- a/src/mainboard/intel/shadowmountain/Kconfig
+++ b/src/mainboard/intel/shadowmountain/Kconfig
@@ -23,7 +23,7 @@
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
select PCIEXP_HOTPLUG
- select SOC_INTEL_ALDERLAKE
+ select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_CSE_LITE_SKU
select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index e5d6d6b..2f8f3da 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -1,12 +1,21 @@
config SOC_INTEL_ALDERLAKE
bool
help
- Intel Alderlake support
+ Intel Alderlake support. Mainboards should specify the PCH
+ type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead
+ of selecting this option directly.
config SOC_INTEL_ALDERLAKE_PCH_M
bool
+ select SOC_INTEL_ALDERLAKE
help
- Choose this option if you have PCH-M chipset.
+ Choose this option if your mainboard has a PCH-M chipset.
+
+config SOC_INTEL_ALDERLAKE_PCH_P
+ bool
+ select SOC_INTEL_ALDERLAKE
+ help
+ Choose this option if your mainboard has a PCH-P chipset.
if SOC_INTEL_ALDERLAKE
@@ -169,12 +178,12 @@
config MAX_PCH_ROOT_PORTS
int
default 10 if SOC_INTEL_ALDERLAKE_PCH_M
- default 12
+ default 12 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_CPU_ROOT_PORTS
int
default 1 if SOC_INTEL_ALDERLAKE_PCH_M
- default 3
+ default 3 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_ROOT_PORTS
int
@@ -183,12 +192,12 @@
config MAX_PCIE_CLOCK_SRC
int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
- default 7
+ default 7 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_PCIE_CLOCK_REQ
int
- default 6 if SOC_INTEL_ALDERLAKE_PCH_M
- default 10
+ default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+ default 10 if SOC_INTEL_ALDERLAKE_PCH_P
config SMM_TSEG_SIZE
hex
diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h
index 0cf334f..059568d 100644
--- a/src/soc/intel/alderlake/include/soc/bootblock.h
+++ b/src/soc/intel/alderlake/include/soc/bootblock.h
@@ -3,6 +3,11 @@
#ifndef _SOC_ALDERLAKE_BOOTBLOCK_H_
#define _SOC_ALDERLAKE_BOOTBLOCK_H_
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) + \
+ CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) != 1
+#error "Please select exactly one PCH type"
+#endif
+
/* Bootblock pre console init programming */
void bootblock_pch_early_init(void);
To view, visit change 59804. To unsubscribe, or for help writing mail filters, visit settings.