Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15490
-gerrit
commit 032a427437eca33dff1f67c4e6af3e80d7652ba9 Author: Aaron Durbin adurbin@chromium.org Date: Tue Jun 28 15:41:07 2016 -0500
soc/intel/{common,skylake}: provide common NHLT SoC support
The nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides() functions should be able to be leveraged on all Intel SoCs which support NHLT. Therefore provide that functionality and make skylake use it.
Change-Id: Ib5535cc874f2680ec22554cecaf97b09753cacd0 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/soc/intel/common/Kconfig | 4 ++++ src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/nhlt.c | 41 +++++++++++++++++++++++++++++++++ src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/nhlt/Makefile.inc | 1 - src/soc/intel/skylake/nhlt/nhlt.c | 41 --------------------------------- 6 files changed, 47 insertions(+), 42 deletions(-)
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index fdd8f04..776004b 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -99,4 +99,8 @@ config SOC_INTEL_COMMON_ACPI bool default n
+config SOC_INTEL_COMMON_NHLT + bool + default n + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 88d5fd2..e9ad508 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -20,6 +20,7 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c
smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c
diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c new file mode 100644 index 0000000..d498152 --- /dev/null +++ b/src/soc/intel/common/nhlt.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <nhlt.h> +#include <soc/acpi.h> + +uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) +{ + return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL); +} + +uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, + uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs == NULL) + return acpi_addr; + + /* Update NHLT GNVS Data */ + gnvs->nhla = (uintptr_t)acpi_addr; + gnvs->nhll = nhlt_current_size(nhlt); + + return nhlt_serialize_oem_overrides(nhlt, acpi_addr, + oem_id, oem_table_id); +} diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index a134d1c..6843cef 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -38,6 +38,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_LPSS_I2C + select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SMM_TSEG select SMP diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index aff182c..e022482 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -1,4 +1,3 @@ -ramstage-y += nhlt.c ramstage-y += dmic.c ramstage-y += nau88l25.c ramstage-y += max98357.c diff --git a/src/soc/intel/skylake/nhlt/nhlt.c b/src/soc/intel/skylake/nhlt/nhlt.c deleted file mode 100644 index d498152..0000000 --- a/src/soc/intel/skylake/nhlt/nhlt.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <nhlt.h> -#include <soc/acpi.h> - -uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) -{ - return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL); -} - -uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, - uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id) -{ - global_nvs_t *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - if (gnvs == NULL) - return acpi_addr; - - /* Update NHLT GNVS Data */ - gnvs->nhla = (uintptr_t)acpi_addr; - gnvs->nhll = nhlt_current_size(nhlt); - - return nhlt_serialize_oem_overrides(nhlt, acpi_addr, - oem_id, oem_table_id); -}