Patch set 7:Code-Review +1
4 comments:
Patch Set #7, Line 14: devices have separate groups
Can you give an example line from before and after?
File src/northbridge/amd/pi/00730F01/northbridge.c:
0xE0 is an index register that provides access to GPP link core registers 0x0140XXXX and IO Link Str […]
Done
File src/northbridge/amd/pi/00730F01/northbridge.c:
Patch Set #7, Line 784: result
results
Patch Set #7, Line 794: value |= (BIT(5) | BIT(6));
If you add macros for these to, you could remove the comment here.
value |= (PI_…_ENABLE_AER | PI_…_ENABLE_ACS)
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