Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35313 )
Change subject: nb/amd/pi/00730F01: enable ACS and AER for PCIe ports ......................................................................
Patch Set 7: Code-Review+1
(4 comments)
https://review.coreboot.org/c/coreboot/+/35313/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35313/7//COMMIT_MSG@14 PS7, Line 14: devices have separate groups Can you give an example line from before and after?
https://review.coreboot.org/c/coreboot/+/35313/2/src/northbridge/amd/pi/0073... File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/35313/2/src/northbridge/amd/pi/0073... PS2, Line 781: 0xB0
0xE0 is an index register that provides access to GPP link core registers 0x0140XXXX and IO Link Str […]
Done
https://review.coreboot.org/c/coreboot/+/35313/7/src/northbridge/amd/pi/0073... File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/35313/7/src/northbridge/amd/pi/0073... PS7, Line 784: result results
https://review.coreboot.org/c/coreboot/+/35313/7/src/northbridge/amd/pi/0073... PS7, Line 794: value |= (BIT(5) | BIT(6)); If you add macros for these to, you could remove the comment here.
value |= (PI_…_ENABLE_AER | PI_…_ENABLE_ACS)