Shreesh Chhabbi uploaded patch set #3 to the change originally created by Shreesh Chhabbi.

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soc/intel/tigerlake: Select USE_CAR_NEM_ENHANCED_V2 for tigerlake

Selects Cache QoS mask MSR programming flow for Tigerlake SoC.

BUG=b:145958015
TEST= Build and boot to Chrome OS on TGL-UP3 RVP.
Recipe used:
1. Patch https://review.coreboot.org/c/coreboot/+/43494 which implements calculation of
CQOS mask dynamically based on stack size usage & incorporates Tigerlake SoC
specific programming flow.
2. QS Engineering Microcode based on 0x56 Official Microcode with LLC CQOS change.
3. QS SoC Part.

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I602d93eb4f8243ec49993b00691140d9a6cf5733
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/45094/3

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