Dave Frodin (dave.frodin@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3348
-gerrit
commit f25e90540bb440832602d497e9c05d6caa007619 Author: Dave Frodin dave.frodin@se-eng.com Date: Fri May 31 08:15:57 2013 -0600
AMD Hudson: Add support for the SD controller
Change-Id: I6d7e7997ddc39802ab75dc8a211ed29f028c0471 Signed-off-by: Dave Frodin dave.frodin@se-eng.com --- src/include/device/pci_ids.h | 1 + src/southbridge/amd/agesa/hudson/Makefile.inc | 1 + src/southbridge/amd/agesa/hudson/chip.h | 1 + src/southbridge/amd/agesa/hudson/sd.c | 79 +++++++++++++++++++++++++++ 4 files changed, 82 insertions(+)
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e9e5ab7..e4e76ca 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -361,6 +361,7 @@ #define PCI_DEVICE_ID_ATI_SB900_USB_19_2 0x7808 #define PCI_DEVICE_ID_ATI_SB900_USB_20_5 0x7809 #define PCI_DEVICE_ID_ATI_SB900_GEC 0x7806 +#define PCI_DEVICE_ID_AMD_YANGTZE_SD 0x7813
#define PCI_DEVICE_ID_ATI_RS690_HT 0x7910 #define PCI_DEVICE_ID_ATI_RS740_HT 0x7911 diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 7802600..80dacdf 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -8,6 +8,7 @@ ramstage-y += sata.c ramstage-y += hda.c ramstage-y += pci.c ramstage-y += pcie.c +ramstage-y += sd.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c diff --git a/src/southbridge/amd/agesa/hudson/chip.h b/src/southbridge/amd/agesa/hudson/chip.h index d54a396..d5f14ff 100644 --- a/src/southbridge/amd/agesa/hudson/chip.h +++ b/src/southbridge/amd/agesa/hudson/chip.h @@ -28,6 +28,7 @@ struct southbridge_amd_agesa_hudson_config u32 boot_switch_sata_ide : 1; u32 hda_viddid; u8 gpp_configuration; + u8 sd_mode; #endif };
diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c new file mode 100644 index 0000000..ad30f14 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/sd.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <delay.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include "hudson.h" + +static void sd_init(struct device *dev) +{ +u32 stepping; + + if (dev->enabled == 0) { + /* turn off the SDHC controller in the PM regs */ + outb(0xE8, PM_INDEX); + outb(0x00, PM_DATA); + return; + } + + stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC); + + dev = dev_find_slot(0, PCI_DEVFN(0x14, 7)); + + struct southbridge_amd_agesa_hudson_config *sd_chip = + (struct southbridge_amd_agesa_hudson_config *)(dev->chip_info); + + if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ + pci_write_config32(dev, 0xA4, 0x31FEC8B2); + pci_write_config32(dev, 0xA8, 0x00002503); + pci_write_config32(dev, 0xB0, 0x02180C19); + pci_write_config32(dev, 0xD0, 0x0000078B); + } + else { /* SD 2.0 mode */ + if ((stepping & 0x0000000F)==0) { /* Stepping A0 */ + pci_write_config32(dev, 0xA4, 0x31DE32B2); + pci_write_config32(dev, 0xB0, 0x01180C19); + pci_write_config32(dev, 0xD0, 0x0000058B); + } + else { /* Stepping >= A1 */ + pci_write_config32(dev, 0xA4, 0x31FE3FB2); + pci_write_config32(dev, 0xB0, 0x01180C19); + pci_write_config32(dev, 0xD0, 0x0000078B); + } + } +} + +static struct device_operations sd_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sd_init, + .scan_bus = 0, +}; + +static const struct pci_driver sd_driver __pci_driver = { + .ops = &sd_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_YANGTZE_SD, +};