1 comment:
File src/soc/intel/tigerlake/romstage/romstage.c:
fsp_memory_init(s3wake);
pmc_set_disb();
if (!s3wake) {
if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
cse_fw_sync();
> Is there a dependency on having FSP-M run before this? The HECI interface was initialized just bef […]
>Yes, from past discussions Intel had mentioned that you cannot run HMRPFO when dram is not initialized. That is the reason this is being done after memory init. I think it would be good to add a comment here.
That's true. I have added comment indicating cse_fw_sync() should be called after DRAM Init.
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