All that said, I respect you and Nico very highly; I don't intend to submit this until I have some feeling I'm not misunderstanding what you are telling me. I regret any bad feelings I might have caused.

Don't worry about the feelings. Let me try to explain what I see
here. This change disables enumeration of all non-mandatory PCI
devices. And you are saying this will be most of the devices in
the `devicetree.cb`. So all later phases of coreboot (which I
estimated as 90% of ramstage) won't know these devices exist.
All code that was written to bring these devices into a state
usable by the OS won't be executed, in the non blob case. And
in the FSP case, we'll violate our contract which says we have
assigned resources to the devices, which we haven't.

These are the most obvious effects, let's not get into details.
Your commit message says, you want to minimize scanning, not
mentioning any of the effects above. So looking at the imple-
mentation, it seems to me, you brought a battle axe to slice
cheese. And while you are already at the third slice, other
people tell me, you are cutting cubes oO

That's why I would like to hear from you, Ron, what is the goal
of this change? Is it about handing over control to the payload
with less resources assigned (what Jeremy asks for)? or is it
about scanning less to reduce boot times? or about doing less
in general? or something entirely else that I miss?

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e
Gerrit-Change-Number: 36221
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