SH Kim has uploaded this change for review.
mb/google/brya/var/xol: Add EC_IN_RW_OD config into early_gpio_table
Add GPP_F18 configuration in early_gpio_table.
Without this, DUT cannot get the proper state of this signal on early
phase. It allowed DUT to attempt to enter into dev mode when EC is in RW
currently, it causes the failure of autotest item - firmware_DevMode.
BUG=b:337365524
TEST=built and run autotest firmware_DevMode
Change-Id: I2179bb10b431547bc35f332c74915a63495b779d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/xol/gpio.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/82099/1
diff --git a/src/mainboard/google/brya/variants/xol/gpio.c b/src/mainboard/google/brya/variants/xol/gpio.c
index 168d982..39478a1 100644
--- a/src/mainboard/google/brya/variants/xol/gpio.c
+++ b/src/mainboard/google/brya/variants/xol/gpio.c
@@ -195,6 +195,8 @@
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+ /* F18 : EC_IN_RW_OD ==> EC_IN_RW_OD */
+ PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
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