Elyes HAOUAS has uploaded this change for review.

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src: Move IA32_ENERGY_PERF_BIAS to x86/msr.h

Change-Id: Ia0b116d4865c1e964e3ebf296cb379a664096c79
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/cpu/intel/fsp_model_206ax/model_206ax.h
M src/cpu/intel/fsp_model_406dx/model_406dx.h
M src/cpu/intel/haswell/haswell.h
M src/cpu/intel/haswell/haswell_init.c
M src/cpu/intel/model_2065x/model_2065x.h
M src/cpu/intel/model_2065x/model_2065x_init.c
M src/cpu/intel/model_206ax/model_206ax.h
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/include/cpu/x86/msr.h
M src/soc/intel/broadwell/cpu.c
M src/soc/intel/broadwell/include/soc/msr.h
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/cannonlake/include/soc/msr.h
M src/soc/intel/denverton_ns/include/soc/msr.h
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/include/soc/msr.h
16 files changed, 16 insertions(+), 48 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/28856/1

diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h
index eb4d6a9..46c7a65 100644
--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h
+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h
@@ -26,10 +26,6 @@
 #define  FLEX_RATIO_EN			(1 << 16)
 #define IA32_PLATFORM_DCA_CAP		0x1f8
 #define MSR_TEMPERATURE_TARGET		0x1a2
-#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
-#define  ENERGY_POLICY_PERFORMANCE	0
-#define  ENERGY_POLICY_NORMAL		6
-#define  ENERGY_POLICY_POWERSAVE	15
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define MSR_LT_LOCK_MEMORY		0x2e7
 #define IA32_MC0_STATUS			0x401
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h
index 194fc12..5d9b8d3 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h
@@ -27,10 +27,6 @@
 #define  FLEX_RATIO_EN			(1 << 16)
 #define IA32_PLATFORM_DCA_CAP		0x1f8
 #define MSR_TEMPERATURE_TARGET		0x1a2
-#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
-#define  ENERGY_POLICY_PERFORMANCE	0
-#define  ENERGY_POLICY_NORMAL		6
-#define  ENERGY_POLICY_POWERSAVE	15
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define MSR_LT_LOCK_MEMORY		0x2e7
 #define IA32_MC0_STATUS			0x401
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index b4e8c88..97c1abe 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -41,10 +41,6 @@
 #define  FLEX_RATIO_EN			(1 << 16)
 #define IA32_PLATFORM_DCA_CAP		0x1f8
 #define MSR_TEMPERATURE_TARGET		0x1a2
-#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
-#define  ENERGY_POLICY_PERFORMANCE	0
-#define  ENERGY_POLICY_NORMAL		6
-#define  ENERGY_POLICY_POWERSAVE	15
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define MSR_LT_LOCK_MEMORY		0x2e7
 #define IA32_MC0_STATUS			0x401
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 5ea8535..3d353ba 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -649,10 +649,10 @@
 		return;
 
 	/* Energy Policy is bits 3:0 */
-	msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
+	msr = rdmsr(IA32_ENERGY_PERF_BIAS);
 	msr.lo &= ~0xf;
 	msr.lo |= policy & 0xf;
-	wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+	wrmsr(IA32_ENERGY_PERF_BIAS, msr);
 
 	printk(BIOS_DEBUG, "haswell: energy policy set to %u\n",
 	       policy);
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index 445d313..aeb113a 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -28,10 +28,6 @@
 #define MSR_TEMPERATURE_TARGET		0x1a2
 #define IA32_FERR_CAPABILITY		0x1f1
 #define   FERR_ENABLE			(1 << 0)
-#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
-#define  ENERGY_POLICY_PERFORMANCE	0
-#define  ENERGY_POLICY_NORMAL		6
-#define  ENERGY_POLICY_POWERSAVE	15
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define IA32_MC0_STATUS			0x401
 
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index 322e814..222c2ed 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -231,10 +231,10 @@
 	msr_t msr;
 
 	/* Energy Policy is bits 3:0 */
-	msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
+	msr = rdmsr(IA32_ENERGY_PERF_BIAS);
 	msr.lo &= ~0xf;
 	msr.lo |= policy & 0xf;
-	wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+	wrmsr(IA32_ENERGY_PERF_BIAS, msr);
 
 	printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n",
 	       policy);
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index cbfa6ae..2f28799 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -26,10 +26,6 @@
 #define  FLEX_RATIO_EN			(1 << 16)
 #define IA32_PLATFORM_DCA_CAP		0x1f8
 #define MSR_TEMPERATURE_TARGET		0x1a2
-#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
-#define  ENERGY_POLICY_PERFORMANCE	0
-#define  ENERGY_POLICY_NORMAL		6
-#define  ENERGY_POLICY_POWERSAVE	15
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define MSR_LT_LOCK_MEMORY		0x2e7
 #define IA32_MC0_STATUS			0x401
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 3cc8d82..194114d 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -401,10 +401,10 @@
 	msr_t msr;
 
 	/* Energy Policy is bits 3:0 */
-	msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
+	msr = rdmsr(IA32_ENERGY_PERF_BIAS);
 	msr.lo &= ~0xf;
 	msr.lo |= policy & 0xf;
-	wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+	wrmsr(IA32_ENERGY_PERF_BIAS, msr);
 
 	printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n",
 	       policy);
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 02c698d..9148349 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -34,6 +34,10 @@
 #define MSR_IA32_MPERF			0xe7
 #define MSR_IA32_APERF			0xe8
 #define IA32_MCG_CAP			0x179
+#define IA32_ENERGY_PERF_BIAS		0x1b0
+#define  ENERGY_POLICY_PERFORMANCE	0
+#define  ENERGY_POLICY_NORMAL		6
+#define  ENERGY_POLICY_POWERSAVE	15
 #define MSR_IA32_PM_ENABLE		0x770
 #define MSR_IA32_HWP_CAPABILITIES	0x771
 #define MSR_IA32_HWP_REQUEST		0x774
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index ee1fd52..4c1b3fd 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -546,10 +546,10 @@
 		return;
 
 	/* Energy Policy is bits 3:0 */
-	msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
+	msr = rdmsr(IA32_ENERGY_PERF_BIAS);
 	msr.lo &= ~0xf;
 	msr.lo |= policy & 0xf;
-	wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+	wrmsr(IA32_ENERGY_PERF_BIAS, msr);
 
 	printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy);
 }
diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h
index 437aef0..40a9340 100644
--- a/src/soc/intel/broadwell/include/soc/msr.h
+++ b/src/soc/intel/broadwell/include/soc/msr.h
@@ -33,10 +33,6 @@
 #define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
 #define MSR_TURBO_RATIO_LIMIT		0x1ad
 #define MSR_TEMPERATURE_TARGET		0x1a2
-#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
-#define  ENERGY_POLICY_PERFORMANCE	0
-#define  ENERGY_POLICY_NORMAL		6
-#define  ENERGY_POLICY_POWERSAVE	15
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define EMRRphysBase_MSR		0x1f4
 #define EMRRphysMask_MSR		0x1f5
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index ba87045..96b82fd 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -126,10 +126,10 @@
 		return;
 
 	/* Energy Policy is bits 3:0 */
-	msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
+	msr = rdmsr(IA32_ENERGY_PERF_BIAS);
 	msr.lo &= ~0xf;
 	msr.lo |= policy & 0xf;
-	wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+	wrmsr(IA32_ENERGY_PERF_BIAS, msr);
 }
 
 static void configure_c_states(void)
diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h
index 86e13ab..f8a342c 100644
--- a/src/soc/intel/cannonlake/include/soc/msr.h
+++ b/src/soc/intel/cannonlake/include/soc/msr.h
@@ -20,10 +20,6 @@
 #include <intelblocks/msr.h>
 
 #define MSR_PIC_MSG_CONTROL		0x2e
-#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
-#define  ENERGY_POLICY_PERFORMANCE	0
-#define  ENERGY_POLICY_NORMAL		6
-#define  ENERGY_POLICY_POWERSAVE	15
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define IA32_PLATFORM_DCA_CAP		0x1f9
 #define MSR_VR_MISC_CONFIG2		0x636
diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h
index d63cc04..58d4cfe 100644
--- a/src/soc/intel/denverton_ns/include/soc/msr.h
+++ b/src/soc/intel/denverton_ns/include/soc/msr.h
@@ -35,10 +35,6 @@
 #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
 #define MSR_TURBO_RATIO_LIMIT 0x1ad
 #define MSR_TEMPERATURE_TARGET 0x1a2
-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
-#define ENERGY_POLICY_PERFORMANCE 0
-#define ENERGY_POLICY_NORMAL 6
-#define ENERGY_POLICY_POWERSAVE 15
 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
 #define EMRR_PHYS_BASE_MSR 0x1f4
 #define EMRR_PHYS_MASK_MSR 0x1f5
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 417c4bc..605dc00 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -353,10 +353,10 @@
 		return;
 
 	/* Energy Policy is bits 3:0 */
-	msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
+	msr = rdmsr(IA32_ENERGY_PERF_BIAS);
 	msr.lo &= ~0xf;
 	msr.lo |= policy & 0xf;
-	wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+	wrmsr(IA32_ENERGY_PERF_BIAS, msr);
 
 	printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy);
 }
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index bfe3671..a371e47 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -24,10 +24,6 @@
 #define  EMULATE_PM_TMR_EN		(1 << 16)
 #define  EMULATE_DELAY_OFFSET_VALUE	20
 #define  EMULATE_DELAY_VALUE		0x13
-#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
-#define  ENERGY_POLICY_PERFORMANCE	0
-#define  ENERGY_POLICY_NORMAL		6
-#define  ENERGY_POLICY_POWERSAVE	15
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define IA32_PLATFORM_DCA_CAP		0x1f8
 #define MSR_LT_LOCK_MEMORY		0x2e7

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