Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33993 )
Change subject: mainboard/amd: Add padmelon board code ......................................................................
Patch Set 17:
(5 comments)
https://review.coreboot.org/c/coreboot/+/33993/15/src/mainboard/amd/padmelon... File src/mainboard/amd/padmelon/Kconfig:
https://review.coreboot.org/c/coreboot/+/33993/15/src/mainboard/amd/padmelon... PS15, Line 61: Select a bit within LPC_IO_PORT_DECODE_ENABLE that will enable : access to IO port HWM_PORT, which is programmed at bootblock.
Left over from Marc. It's hardcoded on the header file, and it's not 100... […]
This was wrong, removed! Correct one is HWM_PORT, which is needed.
https://review.coreboot.org/c/coreboot/+/33993/15/src/mainboard/amd/padmelon... File src/mainboard/amd/padmelon/acpi/gpe.asl:
https://review.coreboot.org/c/coreboot/+/33993/15/src/mainboard/amd/padmelon... PS15, Line 17:
They are, will revisit.
Done
https://review.coreboot.org/c/coreboot/+/33993/15/src/mainboard/amd/padmelon... File src/mainboard/amd/padmelon/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/33993/15/src/mainboard/amd/padmelon... PS15, Line 49: #define SUPERIO_PNP_BASE 0x4E
Ack
It's platform specific, now defined in dsdt.asl.
https://review.coreboot.org/c/coreboot/+/33993/15/src/mainboard/amd/padmelon... File src/mainboard/amd/padmelon/bootblock/OemCustomize.c:
https://review.coreboot.org/c/coreboot/+/33993/15/src/mainboard/amd/padmelon... PS15, Line 162: { 0x10ec0286, AzaliaCodecAlc286Table}, : { 0x10ec0288, AzaliaCodecAlc286Table}, : { 0x10ec0888, AzaliaCodecAlc286Table},
Not sure, again, got from Marc. […]
Done
https://review.coreboot.org/c/coreboot/+/33993/15/src/mainboard/amd/padmelon... File src/mainboard/amd/padmelon/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/33993/15/src/mainboard/amd/padmelon... PS15, Line 70: 0x4E
0x4e is not defined anywhere else, except at devicetree.cb. […]
No response, considered done.