Srinidhi N Kaushik has uploaded this change for review.
src/soc/tigerlake: Update SerialIoDebugMode UPD in FSP-M
Due to refactoring of Serial IO code in FSP v3163 onwards we need to
set SerialIoUartDebugMode UPD in FSP-M to SkipInit so that SerialIoUart
initialization is skipped in FSP. This makes sure that SerialIo
initialization in coreboot is not changed by FSP.
BUG=b:155315876
BRANCH=none
TEST=build and boot tglrvp/ripto/volteer and check UART debug logs
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I8ba4b9015fa25a84b6b99419ce4d413c9d9daa44
---
M src/soc/intel/tigerlake/romstage/fsp_params.c
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/40899/1
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index b4521e2..108a246 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -82,6 +82,7 @@
}
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+ m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit;
/* ISH */
dev = pcidev_path_on_root(PCH_DEVFN_ISH);
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