1 Dec
2022
1 Dec
'22
3:53 p.m.
Attention is currently required from: Stefan Ott, Angel Pons, Arthur Heymans, Alexander Couzens.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69297 )
Change subject: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm ......................................................................
Patch Set 18: Code-Review+2
(1 comment)
File src/northbridge/intel/gm45/northbridge.c:
https://review.coreboot.org/c/coreboot/+/69297/comment/5bac4673_1e79684a PS18, Line 264: __pci_0_00_0
Shall this better be 'pcidev_on_root(0, 0);'? […]
OK, fine with me. I just was wondering since when we have started to use entries from static.c directly.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Gerrit-Change-Number: 69297
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