Duncan Laurie has uploaded this change for review.
drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM
Configure the CFG2 register to set the latency to <64us in order
to ensure the L1 exit latency is consistent across devices and that
L1 ASPM is always enabled.
BUG=b:173207454
TEST=Verify the device and link capability and control for L1:
DevCap: Latency L1 <64us
LnkCap: Latency L1 <64us
LnkCtl: ASPM L1 Enabled
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ie2b85a6697f164fbe4f84d8cd5acb2b5911ca7a9
---
M src/drivers/genesyslogic/gl9755/gl9755.c
M src/drivers/genesyslogic/gl9755/gl9755.h
2 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47682/1
diff --git a/src/drivers/genesyslogic/gl9755/gl9755.c b/src/drivers/genesyslogic/gl9755/gl9755.c
index c3cdef1..ed76457 100644
--- a/src/drivers/genesyslogic/gl9755/gl9755.c
+++ b/src/drivers/genesyslogic/gl9755/gl9755.c
@@ -12,13 +12,23 @@
static void gl9755_init(struct device *dev)
{
+ uint32_t reg;
+
printk(BIOS_INFO, "GL9755: init\n");
pci_dev_init(dev);
/* Set Vendor Config to be configurable */
pci_or_config32(dev, CFG, CFG_EN);
+
/* Set LTR value */
pci_write_config32(dev, LTR, NO_SNOOP_SCALE|NO_SNOOP_VALUE|SNOOP_SCALE|SNOOP_VALUE);
+
+ /* Adjust L1 exit latency to enable ASPM */
+ reg = pci_read_config32(dev, CFG2);
+ reg &= ~CFG2_LAT_L1_MASK;
+ reg |= CFG2_LAT_L1_ASPM;
+ pci_write_config32(dev, CFG2, reg);
+
/* Set Vendor Config to be non-configurable */
pci_and_config32(dev, CFG, ~CFG_EN);
}
diff --git a/src/drivers/genesyslogic/gl9755/gl9755.h b/src/drivers/genesyslogic/gl9755/gl9755.h
index 2d20faf..0492fab 100644
--- a/src/drivers/genesyslogic/gl9755/gl9755.h
+++ b/src/drivers/genesyslogic/gl9755/gl9755.h
@@ -1,11 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef DRIVERS_GENESYSLOGIC_GL9755_H
+#define DRIVERS_GENESYSLOGIC_GL9755_H
+
/* Definitions for Genesys Logic GL9755 */
#define CFG 0x800
#define CFG_EN 0x1
+#define CFG2 0x48
+#define CFG2_LAT_L1_MASK ((0x7 << 12) | (0x7 << 3))
+#define CFG2_LAT_L1_ASPM ((0x6 << 12) | (0x6 << 3))
#define LTR 0x5C
#define SNOOP_VALUE 0x25
#define SNOOP_SCALE (0x3 << 10)
#define NO_SNOOP_VALUE (0x25 << 16)
#define NO_SNOOP_SCALE (0x3 << 26)
+
+#endif /* DRIVERS_GENESYSLOGIC_GL9755_H */
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