1 comment:
File src/northbridge/intel/nehalem/northbridge.c:
Patch Set #4, Line 247: pci_write_config32(dev, D0F0_DEVEN, reg);
I don't like read-modify-write split like this for register D0F0_DEVEN, and having to re-initialise dev. I assume for this hardware there is no write-once registers involved?
"All the bits in this register are Intel TXT Lockable." We don't seem to do that at the moment, but I don't like disabling/hiding devices after the resource allocation has been done.
I think moving this before the raminit might be appropriate? Early ramstage like gm45 does it, is also an option.
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