Lean Sheng Tan has uploaded this change for review.
soc/intel/elkhartlake: Add FSP-T support
1. Add FSP-T related UPD settings in bootblock.c
2. Set FSP-T as default
3. Add choice option to select CAR implementation
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I7d7f14e4e8be8755e01d9a3988608d5d47145496
---
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/bootblock/bootblock.c
2 files changed, 61 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/45079/1
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index b5462ff..fc67372 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -24,7 +24,6 @@
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
- select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select IOAPIC
@@ -61,6 +60,7 @@
select UDELAY_TSC
select UDK_202005_BINDING
select DISPLAY_FSP_VERSION_INFO
+ select FSP_T_XIP if FSP_CAR
config DCACHE_RAM_BASE
default 0xfef00000
@@ -183,6 +183,30 @@
hex
default 0x200000
+choice
+ prompt "Cache-as-ram implementation"
+ default USE_ELKHARTLAKE_FSP_CAR
+ help
+ This option allows you to select how cache-as-ram (CAR) is set up.
+
+config USE_ELKHARTLAKE_CAR_NEM
+ bool "Enhanced Non-evict mode"
+ select INTEL_CAR_NEM
+ help
+ A current limitation of NEM (Non-Evict mode) is that code and data
+ sizes are derived from the requirement to not write out any modified
+ cache line. With NEM, if there is no physical memory behind the
+ cached area, the modified data will be lost and NEM results will be
+ inconsistent.
+
+config USE_ELKHARTLAKE_FSP_CAR
+ bool "Use FSP CAR"
+ select FSP_CAR
+ help
+ Use FSP APIs to initialize and tear down the Cache-As-Ram.
+
+endchoice
+
config FSP_HEADER_PATH
default "src/vendorcode/intel/fsp/fsp2_0/elkhartlake/"
diff --git a/src/soc/intel/elkhartlake/bootblock/bootblock.c b/src/soc/intel/elkhartlake/bootblock/bootblock.c
index 96e6268..d6e20ca 100644
--- a/src/soc/intel/elkhartlake/bootblock/bootblock.c
+++ b/src/soc/intel/elkhartlake/bootblock/bootblock.c
@@ -6,6 +6,42 @@
#include <intelblocks/uart.h>
#include <soc/bootblock.h>
+#if CONFIG(FSP_CAR)
+#include <FsptUpd.h>
+
+const FSPT_UPD temp_ram_init_params = {
+ .FspUpdHeader = {
+ .Signature = 0x545F4450554C4845ULL, /* 'EHLUPD_T' */
+ .Revision = 1,
+ .Reserved = {0},
+ },
+ .FsptCoreUpd = {
+ .MicrocodeRegionBase = 0,
+ .MicrocodeRegionSize = 0,
+ .CodeRegionBase = 0xff000000,
+ .CodeRegionSize = 0x1000000,
+ },
+ .FsptConfig = {
+ .PcdSerialIoUartDebugEnable = 1,
+ .PcdSerialIoUartNumber = 2,
+ .PcdSerialIoUartMode = 2,
+ .PcdSerialIoUartBaudRate = 115200,
+ .PcdPciExpressBaseAddress = 0xc0000000,
+ .PcdPciExpressRegionLength = 0x10000000,
+ .PcdSerialIoUartParity = 1,
+ .PcdSerialIoUartDataBits = 8,
+ .PcdSerialIoUartStopBits = 1,
+ .PcdSerialIoUartAutoFlow = 0,
+ .PcdSerialIoUartRxPinMux = 0,
+ .PcdSerialIoUartTxPinMux = 0,
+ .PcdSerialIoUartRtsPinMux = 0,
+ .PcdSerialIoUartCtsPinMux = 0,
+ .PcdLpcUartDebugEnable = 1,
+ },
+ .UpdTerminator = 0x55AA,
+};
+#endif
+
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
/* Call lib/bootblock.c main */
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