awokd@danwin1210.me has uploaded this change for review.

View Change

vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze: Remove redundant FIS code

From looking at neighboring code, disabling FIS based switching appears
intentional, possibly due to errata. Clean and comment code so it is
apparent.

Change-Id: I4529716e951a9e7b63bdee11611dd78f2d41b464
Signed-off-by: Joe Moore <awokd@danwin1210.me>
---
M src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c
1 file changed, 4 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/36001/1

diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c
index 9f526d8..293ea57 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c
@@ -367,11 +367,8 @@
     AndMaskDword |= BIT12;
   }
 
-  if ( FchSataFisBasedSwitching ) {
-      AndMaskDword |= BIT10;
-  } else {
-    AndMaskDword |= BIT10;
-  }
+  // FchSataFisBasedSwitching
+  AndMaskDword |= BIT10;
 
   if ( FchSataAggrLinkPmCap ) {
     OrMaskDword |= BIT11;
@@ -431,11 +428,8 @@
     RwMem ((Bar5 + 0x0FC), AccessWidth32, (UINT32)~(BIT20), 0x00);
   }
 
-  if ( FchSataFisBasedSwitching ) {
-      RwMem ((Bar5 + 0x0F8), AccessWidth32, 0x00FFFFFF, 0x00);
-  } else {
-    RwMem ((Bar5 + 0x0F8), AccessWidth32, 0x00FFFFFF, 0x00);
-  }
+  // FchSataFisBasedSwitching
+  RwMem ((Bar5 + 0x0F8), AccessWidth32, 0x00FFFFFF, 0x00);
 
   if ( LocalCfgPtr->Sata.BiosOsHandOff == 1 ) {
     RwMem ((Bar5 + 0x24), AccessWidth8, (UINT32)~BIT0, BIT0);

To view, visit change 36001. To unsubscribe, or for help writing mail filters, visit settings.