[coreboot-gerrit] Patch set updated for coreboot: f6915f5 exynos5420: add CPLL and DPLL to the known list of PLLs

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4461

-gerrit

commit f6915f52f61faeb5a64dc2d77db7d0abe59689e4
Author: David Hendricks 
Date:   Thu Aug 8 16:16:40 2013 -0700

exynos5420: add CPLL and DPLL to the known list of PLLs

This patch adds CPLL and DPLL to the known list of PLLs.

This is ported from https://gerrit.chromium.org/gerrit/#/c/62617/

Signed-off-by: David Hendricks

Change-Id: I2f2614e44cd9c98d98b8db9347f29de21703d1af
    Reviewed-on: https://gerrit.chromium.org/gerrit/65282
    Reviewed-by: Gabe Black 
    Tested-by: David Hendricks 
    Commit-Queue: David Hendricks 
---
 src/cpu/samsung/exynos5420/clk.h   | 2 ++
 src/cpu/samsung/exynos5420/clock.c | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h
index a4e538d..b37c076 100644
--- a/src/cpu/samsung/exynos5420/clk.h
+++ b/src/cpu/samsung/exynos5420/clk.h
@@ -33,6 +33,8 @@ enum periph_id;
 #define BPLL	5
 #define RPLL	6
 #define SPLL	7
+#define CPLL	8
+#define DPLL	9

enum pll_src_bit {
    EXYNOS_SRC_CPLL = 1,
diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c
index ed5b102..b8e27ff 100644
--- a/src/cpu/samsung/exynos5420/clock.c
+++ b/src/cpu/samsung/exynos5420/clock.c
@@ -103,6 +103,12 @@ unsigned long get_pll_clk(int pllreg)
    case SPLL:
    	r = readl(&clk->spll_con0);
    	break;
+	case CPLL:
+		r = readl(&clk->cpll_con0);
+		break;
+	case DPLL:
+		r = readl(&clk->dpll_con0);
+		break;
    default:
    	printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg);
    	return 0;