Julius Werner submitted this change.

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trogdor: mainboard reference all QUPv3 FW drivers

Change-Id: I8ff5dd63fac28ffa558aec71e79a6de87d7885e0
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37306
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/google/trogdor/bootblock.c
M src/mainboard/google/trogdor/mainboard.c
2 files changed, 40 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/trogdor/bootblock.c b/src/mainboard/google/trogdor/bootblock.c
index 05e53a6..b17c2e7 100644
--- a/src/mainboard/google/trogdor/bootblock.c
+++ b/src/mainboard/google/trogdor/bootblock.c
@@ -2,8 +2,12 @@
 
 #include <bootblock_common.h>
 #include "board.h"
+#include <soc/qcom_qup_se.h>
+#include <soc/qupv3_spi.h>
 
 void bootblock_mainboard_init(void)
 {
 	setup_chromeos_gpios();
+	qup_spi_init(QUPV3_1_SE0, 1010 * KHz); /* H1 SPI */
+	qup_spi_init(QUPV3_0_SE0, 1010 * KHz); /* EC SPI */
 }
diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c
index 2ac5659..c82eaa0 100644
--- a/src/mainboard/google/trogdor/mainboard.c
+++ b/src/mainboard/google/trogdor/mainboard.c
@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
-#include <device/mmio.h>
-#include <gpio.h>
-#include <timestamp.h>
+#include <soc/qupv3_config.h>
 #include <soc/usb.h>
 
 static struct usb_board_data usb0_board_data = {
@@ -17,9 +15,44 @@
 	setup_usb_host0(&usb0_board_data);
 }
 
+static void qi2s_configure_gpios(void)
+{
+
+	gpio_configure(GPIO(49), GPIO49_FUNC_MI2S_1_SCK,
+				GPIO_PULL_UP, GPIO_8MA, GPIO_OUTPUT);
+
+	gpio_configure(GPIO(50), GPIO50_FUNC_MI2S_1_WS,
+				GPIO_PULL_UP, GPIO_8MA, GPIO_OUTPUT);
+
+	gpio_configure(GPIO(51), GPIO51_FUNC_MI2S_1_DATA0,
+				GPIO_PULL_UP, GPIO_8MA, GPIO_OUTPUT);
+}
+
+static void load_qup_fw(void)
+{
+	qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_SPI, MIXED);  /* ESIM SPI */
+	qupv3_se_fw_load_and_init(QUPV3_0_SE2, SE_PROTOCOL_I2C, MIXED);  /* EDP Bridge I2C */
+	qupv3_se_fw_load_and_init(QUPV3_0_SE3, SE_PROTOCOL_UART, FIFO);  /* BT UART */
+	qupv3_se_fw_load_and_init(QUPV3_0_SE4, SE_PROTOCOL_I2C, MIXED);  /* Pen Detect I2C */
+	qupv3_se_fw_load_and_init(QUPV3_0_SE5, SE_PROTOCOL_I2C, MIXED);  /* SAR I2C */
+	qupv3_se_fw_load_and_init(QUPV3_1_SE1, SE_PROTOCOL_I2C, MIXED);  /* Trackpad I2C */
+	/*
+	 * When coreboot firmware disables serial output,
+	 * we still need to load console UART QUP FW for OS.
+	 */
+	if (!CONFIG(CONSOLE_SERIAL))
+		qupv3_se_fw_load_and_init(QUPV3_1_SE2, SE_PROTOCOL_UART, FIFO);
+
+	qupv3_se_fw_load_and_init(QUPV3_1_SE3, SE_PROTOCOL_I2C, MIXED);  /* Speaker Amps I2C */
+	qupv3_se_fw_load_and_init(QUPV3_1_SE4, SE_PROTOCOL_SPI, MIXED);  /* Fingerprint SPI */
+	qupv3_se_fw_load_and_init(QUPV3_1_SE5, SE_PROTOCOL_I2C, MIXED);  /* Codec I2C */
+}
+
 static void mainboard_init(struct device *dev)
 {
 	setup_usb();
+	qi2s_configure_gpios();
+	load_qup_fw();
 }
 
 static void mainboard_enable(struct device *dev)

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