2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.


mb/google/brox: Move storage devices to overridetree

These are specific to the brox board, so moving devices to the brox
variant.

BUG=b:311450057,b:300690448,b:319058143
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
     will check if this helps detect the storage device in the factory

Change-Id: I18d096040c293abfd4cd0b1bb5f50ba6dcc2e183
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
M src/mainboard/google/brox/variants/brox/overridetree.cb
2 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
index f824473..5589bbe 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
+++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
@@ -187,21 +187,6 @@
 		end
 		device ref heci1 on end
 		device ref sata on end
-		device ref pcie4_0 on
-			# Enable CPU PCIE RP 1 using CLK 3
-			register "cpu_pcie_rp[CPU_RP(1)]" = "{
-				.clk_req = 3,
-				.clk_src = 3,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-		device ref ish on
-			chip drivers/intel/ish
-				register "add_acpi_dma_property" = "true"
-				device generic 0 on end
-			end
-		end
-		device ref ufs on end
 		device ref uart0 on end
 		device ref gspi1 on end
 		device ref pch_espi on
diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb
index 4aaaf5f..0086099 100644
--- a/src/mainboard/google/brox/variants/brox/overridetree.cb
+++ b/src/mainboard/google/brox/variants/brox/overridetree.cb
@@ -172,5 +172,24 @@
 				device generic 0 on end
 			end
 		end
+		device ref pcie4_0 on
+			# Enable CPU PCIE RP 1 using CLK 3
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_req = 3,
+				.clk_src = 3,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			probe STORAGE STORAGE_NVME
+		end
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+			probe STORAGE STORAGE_UFS
+		end
+		device ref ufs on
+			probe STORAGE STORAGE_UFS
+		end
 	end
 end

