Tim Wawrzynczak uploaded patch set #4 to this change.

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soc/intel/common/block: Add new block DTT

Intel Dynamic Tuning Technology is the name of a PCI device on some
Intel SoCs. This minimal PCI driver is only used now for SSDT generation
on TGL devices.

Change-Id: Ib52f35e4e020ca3e6ab8b32cc3bf7df36041926e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
M src/include/device/pci_ids.h
A src/soc/intel/common/block/dtt/Kconfig
A src/soc/intel/common/block/dtt/Makefile.inc
A src/soc/intel/common/block/dtt/dtt.c
M src/soc/intel/tigerlake/Kconfig
5 files changed, 37 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/41893/4

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib52f35e4e020ca3e6ab8b32cc3bf7df36041926e
Gerrit-Change-Number: 41893
Gerrit-PatchSet: 4
Gerrit-Owner: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth@google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: newpatchset