Shelley Chen has uploaded this change for review.
mb/google/hatch: Use MEM_CH_SEL to indicate single_channel sku
MEM_CH_SEL is used to indicate whether we are on a single or dual
channel device, where MEM_CH_SEL = 1 for single channel skus and
MEM_CH_SEL = 0 for dual channel skus. Initialize MemorySpdPrt
pointers based on the value read from MEM_CH_SEL, which is read from
GPP_F2. In the first build, we did not use GPP_F2, so we need to add
an internal pulldown as those early devices were all dual channel
devices.
BUG=b:123062346, b:122959294
BRANCH=None
TEST=Boot into current boards and ensure that we have 2 channels as expected
Also, verify that GPP_F2 is set to 0.
Change-Id: I89d022793580be603a93d0b177d73ce968529b5c
Signed-off-by: Shelley Chen <shchen@google.com>
---
M src/mainboard/google/hatch/romstage.c
M src/mainboard/google/hatch/variants/baseboard/gpio.c
M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/hatch/variants/baseboard/memory.c
4 files changed, 47 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/31358/1
diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c
index 401f41f..b2db7ee 100644
--- a/src/mainboard/google/hatch/romstage.c
+++ b/src/mainboard/google/hatch/romstage.c
@@ -19,11 +19,14 @@
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
+ struct cnl_mb_cfg memcfg;
+
const struct spd_info spd = {
.spd_by_index = true,
.spd_spec.spd_index = variant_memory_sku(),
};
+ variant_memory_params(&memcfg);
cannonlake_memcfg_init(&memupd->FspmConfig,
- variant_memory_params(), &spd);
+ &memcfg, &spd);
}
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index f8d5d7d..b87cfa8 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -115,6 +115,8 @@
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
/* WWAN_RESET_1V8_ODL */
PAD_CFG_GPO(GPP_F1, 1, DEEP),
+ /* MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_F2, DN_20K, PLTRST),
/* UART_WWANTX_WLANRX_COEX1 */
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
/* UART_WWANRX_WLANTX_COEX2 */
@@ -185,6 +187,8 @@
PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
/* WLAN_PE_RST# */
PAD_CFG_GPO(GPP_C23, 1, DEEP),
+ /* MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_F2, DN_20K, PLTRST),
};
const struct pad_config *__weak variant_early_gpio_table(size_t *num)
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
index 038ec6e..aa7c67d 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
@@ -16,6 +16,7 @@
#ifndef BASEBOARD_VARIANTS_H
#define BASEBOARD_VARIANTS_H
+#include <soc/cnl_memcfg_init.h>
#include <soc/gpio.h>
#include <stdint.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -29,7 +30,7 @@
int variant_memory_sku(void);
/* Return board specific memory configuration */
-const struct cnl_mb_cfg *variant_memory_params(void);
+void variant_memory_params(struct cnl_mb_cfg *bcfg);
/* Return ChromeOS gpio table and fill in number of entries. */
const struct cros_gpio *variant_cros_gpios(size_t *num);
diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c
index 80f3ba4..977573d 100644
--- a/src/mainboard/google/hatch/variants/baseboard/memory.c
+++ b/src/mainboard/google/hatch/variants/baseboard/memory.c
@@ -18,33 +18,46 @@
#include <gpio.h>
#include <soc/cnl_memcfg_init.h>
-static const struct cnl_mb_cfg baseboard_memcfg = {
- /*
- * The dqs_map arrays map the ddr4 pins to the SoC pins
- * for both channels.
- *
- * the index = pin number on ddr4 part
- * the value = pin number on SoC
- */
- .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 },
- .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 },
-
- /* Baseboard uses 120, 81 and 100 rcomp resistors */
- .rcomp_resistor = { 120, 81, 100 },
-
- /* Baseboard Rcomp target values */
- .rcomp_targets = { 100, 40, 20, 20, 26 },
-
- /* Set CaVref config to 2 */
- .vref_ca_config = 2,
-
- /* Enable Early Command Training */
- .ect = 1,
+/*
+ * The dqs_map arrays map the ddr4 pins to the SoC pins
+ * for both channels.
+ *
+ * the index = pin number on ddr4 part
+ * the value = pin number on SoC
+ */
+static const uint8_t dqs_map_ddr4[][8] = {
+ { 0, 1, 4, 5, 2, 3, 6, 7 },
+ { 0, 1, 4, 5, 2, 3, 6, 7 }
};
+/* Baseboard uses 120, 81 and 100 rcomp resistors */
+const static uint16_t rcomp_resistor_ddr4[] = { 120, 81, 100 };
+/* Baseboard Rcomp target values */
+const static uint16_t rcomp_targets_ddr4[] = { 100, 40, 20, 20, 26 };
-const struct cnl_mb_cfg *__weak variant_memory_params(void)
+void __weak variant_memory_params(struct cnl_mb_cfg *bcfg)
{
- return &baseboard_memcfg;
+ int i;
+
+ for (i = 0; i < sizeof(dqs_map_ddr4[DDR_CH0])/sizeof(uint8_t); i++) {
+ bcfg->dqs_map[DDR_CH0][i] = dqs_map_ddr4[DDR_CH0][i];
+ bcfg->dqs_map[DDR_CH1][i] = dqs_map_ddr4[DDR_CH1][i];
+ }
+
+ for (i = 0; i < sizeof(rcomp_resistor_ddr4)/sizeof(uint16_t); i++)
+ bcfg->rcomp_resistor[i] = rcomp_resistor_ddr4[i];
+
+ for (i = 0; i < sizeof(rcomp_targets_ddr4)/sizeof(uint16_t); i++)
+ bcfg->rcomp_targets[i] = rcomp_targets_ddr4[i];
+
+ bcfg->vref_ca_config = 2;
+ bcfg->ect = 1;
+
+ /*
+ * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single
+ * channel skus and 0 for dual channel skus.
+ */
+ if (gpio_get(GPP_F2) == 1)
+ bcfg->single_channel = 1;
}
int __weak variant_memory_sku(void)
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