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• File src/soc/intel/tigerlake/romstage/romstage.c:

  • Patch Set #4, Line 136:

    	fsp_memory_init(s3wake);
    	pmc_set_disb();
    	if (!s3wake) {
    		if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
    			cse_fw_sync();
    

    Is there a dependency on having FSP-M run before this? The HECI interface was initialized just befor […]

    Is the MRC cache data written back to the SPI ROM before CSE FW Sync. Otherwise, there might be more training.

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