soc/intel/common: Call pci_dev_request_bus_master() from .final ops

Enable PCI_COMMAND_MASTER for graphics, storage and host bridge PCI
controller to ensure device can behave as a bus master.
Otherwise, the device can not generate PCI accesses.

This patch ensures that coreboot would set PCI_COMMAND_MASTER at end of
POST to be independent of FSP supported IA-platform where FSP might
clear PCI_COMMAND_MASTER accidentally and payload won't be able to
access the PCI device resources hence leads to unnecessary delay or
even timeout.

BUG=b:154900210
TEST=Able to build and boot CML and TGL platform.

Change-Id: Ife65f6029d2f966e321f616e85f59f4c37c42145
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/xhci/xhci.c
7 files changed, 7 insertions(+), 7 deletions(-)