Anonymous Coward (1001664) has uploaded this change for review.

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riscv: temporarily block multiple-threads

Sometime needs to temporarily block multiple-threads.
So add this code.

Change-Id: Iedf58db6cddd44cfc17f5dfb3a5ccc0e12a49536
Signed-off-by: Xiang Wang <wxjstz@126.com>
---
A src/arch/riscv/include/smp.h
1 file changed, 56 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/27348/1

diff --git a/src/arch/riscv/include/smp.h b/src/arch/riscv/include/smp.h
new file mode 100644
index 0000000..6253768
--- /dev/null
+++ b/src/arch/riscv/include/smp.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2013, The Regents of the University of California (Regents).
+ * All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Regents nor the
+ *    names of its contributors may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+ * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
+ * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
+ * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
+ */
+
+#ifndef _SMP_H
+#define _SMP_H
+
+#include <atomic.h>
+
+#define barrier() {asm volatile ("fence" ::: "memory"); }
+
+/*
+ * If your code needs to temporarily block multiple-threads, do this:
+ *      if(RUNNING_ON_HART(active)) // `active` is hartid of working thread
+ *      {
+ *          ... single-threaded work ...
+ *      }
+ *      SMP_SYNC();
+ *      //`SMP_SYNC` is optional.
+ *      // if other hart need to wait for the single-threaded work to complete.
+ *  ... multi-threaded work ...
+ */
+
+
+#define RUNNING_ON_HART(active) ((active) == read_csr(mhartid))
+
+#define SMP_SYNC()  do {\
+static int counter;\
+atomic_add(&counter, 1);\
+do { barrier(); } while (counter < CONFIG_HART_NUM);\
+} while (0)
+
+#endif //_SMP_H

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