1 comment:
File src/soc/intel/alderlake/romstage/fsp_params.c:
Patch Set #22, Line 158: /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
we need to read the CpuPcieRpEnableMask value with and without this CL.
My meaning is CpuPcieRpEnableMask depends on SA_DEVFN_CPU_PCIE? The UPD said this is each port per bit. But is_dev_enabled(dev) is only one bit, is this correct??
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