Brandon Breitenstein (brandon.breitenstein@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15937
-gerrit
commit 2c02344f998c334c682809c1a191cd143117ce1a Author: Brandon Breitenstein brandon.breitenstein@intel.com Date: Mon Jul 18 15:14:12 2016 -0700
oc/intel/apollolake: Enable ELOG for APL
add in the base for ELOG for APL. Some PM events still need to be added but the basic events are logged here. This enables the basic functionality of ELOG for apollolake.
Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/elog.c | 109 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/pm.h | 2 + 3 files changed, 112 insertions(+)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 9e30df8..3ea2762 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -48,6 +48,7 @@ smm-y += uart_early.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c ramstage-y += chip.c +ramstage-y += elog.c ramstage-y += dsp.c ramstage-y += gpio.c ramstage-y += graphics.c diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c new file mode 100644 index 0000000..dc75859 --- /dev/null +++ b/src/soc/intel/apollolake/elog.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <cbmem.h> +#include <console/console.h> +#include <stdint.h> +#include <elog.h> +#include <soc/pm.h> +#include <soc/pci_devs.h> + +static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) +{ + int i; + + gpe0_sts &= gpe0_en; + + for (i = 0; i <= 31; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + } +} + +static void pch_log_wake_source(struct chipset_power_state *ps) +{ + /* Power Button */ + if (ps->pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + /* RTC */ + if (ps->pm1_en & RTC_EN) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + /* PCI Express (TODO: determine wake device) */ + if (ps->pm1_en & PCIEXPWAK_DIS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + + /* Internal PME (TODO: determine wake device) */ + if (ps->gpe0_sts[PMC_GPE_NW_31_0] & PME_B0_EN) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + + + /* Log GPIO events in set 1-3 */ + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_31_0], ps->gpe0_en[PMC_GPE_SW_31_0], 0); + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_63_32], ps->gpe0_en[PMC_GPE_SW_63_32], 32); + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_95_64], ps->gpe0_en[PMC_GPE_SW_95_64], 64); +} + +static void pch_log_power_and_resets(struct chipset_power_state *ps) +{ + + /* PWR_FLR Power Failure */ + if (ps->gen_pmcon1 & PWR_FLR) + elog_add_event(ELOG_TYPE_POWER_FAIL); + + /* SUS Well Power Failure */ + if (ps->gen_pmcon1 & SUS_PWR_FLR) + elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); + + /* RTC Reset */ + if (ps->gen_pmcon2 & RPS) + elog_add_event(ELOG_TYPE_RTC_RESET); + + /* TCO Timeout */ + if (ps->prev_sleep_state != 3 && + ps->tco_sts & TCO_TIMEOUT) + elog_add_event(ELOG_TYPE_TCO_RESET); + + /* Power Button Override */ + if (ps->pm1_sts & PRBTNOR_STS) + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + + /* ACPI Wake Event */ + if (ps->prev_sleep_state != SLEEP_STATE_S0) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); +} + +static void pch_log_state(void *unused) +{ + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (ps == NULL) { + printk(BIOS_ERR, + "Not logging power state information. Power state not found in cbmem.\n"); + return; + } + + /* Power and Reset */ + pch_log_power_and_resets(ps); + + /* Wake Sources */ + if (ps->prev_sleep_state > 0) + pch_log_wake_source(ps); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL); diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index d8eb50b..aef255b 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -25,6 +25,7 @@
#define PM1_STS 0x00 #define WAK_STS (1 << 15) +#define PRBTNOR_STS (1 << 11) #define PWRBTN_STS (1 << 8)
#define PM1_EN 0x02 @@ -138,6 +139,7 @@
#define PMC_GPE_SW_31_0 0 #define PMC_GPE_SW_63_32 1 +#define PMC_GPE_SW_95_64 2 #define PMC_GPE_NW_31_0 3 #define PMC_GPE_NW_63_32 4 #define PMC_GPE_NW_95_64 5