Subrata Banik has uploaded this change for review.
soc/intel/cannonlake: Disable ACPI PM Timer to enable XTAL OSC shutdown
Keeping ACPI PM timer alive prevents XTAL OSC shutdown in S0ix
which has a power impact.
BRANCH=none
BUG=b:138152075
TEST=Build for cometlake board with the PmTimerDisabled policy in
devicetree set to 1.
Change-Id: I347c15c7b65fb4c19b9680f127980d4ddab8df51
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34506/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 6ff90f8..eb4be43 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -47,6 +47,8 @@
# Unlock GPIO pads
register "PchUnlockGpioPads" = "1"
+ register "PmTimerDisabled" = "1"
+
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index cbaa710..6a2c038 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -366,6 +366,9 @@
params->PchPwrOptEnable = config->dmipwroptimize;
params->SataPwrOptEnable = config->satapwroptimize;
+ /* Disable PCH ACPI timer */
+ params->EnableTcoTimer = !config->PmTimerDisabled;
+
/* Apply minimum assertion width settings if non-zero */
if (config->PchPmSlpS3MinAssert)
params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;
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