[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Add required FSP UPD changes for CML

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31284 )

Change subject: soc/intel/cannonlake: Add required FSP UPD changes for CML
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Patch Set 16:

(1 comment)

https://review.coreboot.org/#/c/31284/15/src/soc/intel/cannonlake/include/so... 
File src/soc/intel/cannonlake/include/soc/serialio.h:

https://review.coreboot.org/#/c/31284/15/src/soc/intel/cannonlake/include/so... 
PS15, Line 35: #endif
> PchSerialIoLegacyUart was introduced from CML FSP code and it is used to communicate to FSP that UAR […]

I still doubt that anything changed (beside the additional `SkipInit`).
We have for CML:

0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,                    
    4:SerialIoUartSkipInit

and for CNL/CFL:

0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode)

Maybe my interpretation is wrong, but in "Acpi mode", I'd expect the PCI
device to be hidden (much like `SerialIoUartHidden`), both have a value
of 2. Legacy serial ports were also called COM ports, hence "Hidden mode
(Legacy UART mode)" and `SerialIoUartCom` seem the same to me, too, both
with a value of 3.