Lijian Zhao has uploaded this change for review.
soc/intel/cannonlake: Add northbridge dsdt table
Add ACPI dsdt table for northbridge, report proper resources in dsdt
entries.
TEST=Boot up into OS fine.
Change-Id: I382d87da087ae7828eaa7ff28bc9597a332ca5bc
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
---
A src/soc/intel/cannonlake/Kconfig.orig
M src/soc/intel/cannonlake/acpi/northbridge.asl
M src/soc/intel/cannonlake/include/soc/iomap.h
3 files changed, 473 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/21756/1
diff --git a/src/soc/intel/cannonlake/Kconfig.orig b/src/soc/intel/cannonlake/Kconfig.orig
new file mode 100644
index 0000000..dd1798d
--- /dev/null
+++ b/src/soc/intel/cannonlake/Kconfig.orig
@@ -0,0 +1,148 @@
+config SOC_INTEL_CANNONLAKE
+ bool
+ help
+ Intel Cannonlake support
+
+if SOC_INTEL_CANNONLAKE
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_VERSTAGE_X86_32
+ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
+ select BOOT_DEVICE_SUPPORTS_WRITES
+ select C_ENVIRONMENT_BOOTBLOCK
+ select COMMON_FADT
+ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+ select GENERIC_GPIO_LIB
+ select HAVE_FSP_GOP
+ select HAVE_HARD_RESET
+ select HAVE_INTEL_FIRMWARE
+ select HAVE_MONOTONIC_TIMER
+ select INTEL_CAR_NEM_ENHANCED
+<<<<<<< HEAD
+ select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
+=======
+ select IOAPIC
+>>>>>>> 2e775ac... [wip]soc/intel/cannonlake: Add lpc pci driver
+ select PARALLEL_MP
+ select PARALLEL_MP_AP_WORK
+ select PLATFORM_USES_FSP2_0
+ select POSTCAR_CONSOLE
+ select POSTCAR_STAGE
+ select REG_SCRIPT
+ select RELOCATABLE_RAMSTAGE
+ select SMP
+ select SOC_INTEL_COMMON
+ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+ select SOC_INTEL_COMMON_BLOCK
+ select SOC_INTEL_COMMON_BLOCK_ACPI
+ select SOC_INTEL_COMMON_BLOCK_CAR
+ select SOC_INTEL_COMMON_BLOCK_CPU
+ select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
+ select SOC_INTEL_COMMON_BLOCK_CSE
+ select SOC_INTEL_COMMON_BLOCK_FAST_SPI
+ select SOC_INTEL_COMMON_BLOCK_GPIO
+ select SOC_INTEL_COMMON_BLOCK_GSPI
+ select SOC_INTEL_COMMON_BLOCK_ITSS
+ select SOC_INTEL_COMMON_BLOCK_LPC
+ select SOC_INTEL_COMMON_BLOCK_LPSS
+ select SOC_INTEL_COMMON_BLOCK_PCR
+ select SOC_INTEL_COMMON_BLOCK_PMC
+ select SOC_INTEL_COMMON_BLOCK_RTC
+ select SOC_INTEL_COMMON_BLOCK_SA
+ select SOC_INTEL_COMMON_BLOCK_SMBUS
+ select SOC_INTEL_COMMON_BLOCK_SMM
+ select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
+ select SOC_INTEL_COMMON_BLOCK_TIMER
+ select SOC_INTEL_COMMON_BLOCK_UART
+ select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
+ select SOC_INTEL_COMMON_RESET
+ select SUPPORT_CPU_UCODE_IN_CBFS
+ select TSC_CONSTANT_RATE
+ select TSC_MONOTONIC_TIMER
+ select UDELAY_TSC
+
+config UART_DEBUG
+ bool "Enable UART debug port."
+ default y
+ select CONSOLE_SERIAL
+ select BOOTBLOCK_CONSOLE
+ select DRIVERS_UART
+ select DRIVERS_UART_8250MEM_32
+ select NO_UART_ON_SUPERIO
+
+config UART_FOR_CONSOLE
+ int "Index for LPSS UART port to use for console"
+ default 2 if DRIVERS_UART_8250MEM
+ default 0
+ help
+ Index for LPSS UART port to use for console:
+ 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
+
+config DCACHE_RAM_BASE
+ default 0xfef00000
+
+config DCACHE_RAM_SIZE
+ default 0x40000
+ help
+ The size of the cache-as-ram region required during bootblock
+ and/or romstage.
+
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x4000
+ help
+ The amount of anticipated stack usage in CAR by bootblock and
+ other stages.
+
+config IED_REGION_SIZE
+ hex
+ default 0x400000
+
+config MAX_ROOT_PORTS
+ int
+ default 24
+
+config SMM_TSEG_SIZE
+ hex
+ default 0x800000
+
+config PCR_BASE_ADDRESS
+ hex
+ default 0xfd000000
+ help
+ This option allows you to select MMIO Base Address of sideband bus.
+
+config CPU_BCLK_MHZ
+ int
+ default 100
+
+config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
+ int
+ default 3
+
+# Clock divider parameters for 115200 baud rate
+config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
+ hex
+ default 0x30
+
+config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
+ hex
+ default 0xc35
+
+config CHROMEOS
+ select CHROMEOS_RAMOOPS_DYNAMIC
+
+config VBOOT
+ select VBOOT_SEPARATE_VERSTAGE
+ select VBOOT_OPROM_MATTERS
+ select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
+ select VBOOT_STARTS_IN_BOOTBLOCK
+ select VBOOT_VBNV_CMOS
+ select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
+
+endif
diff --git a/src/soc/intel/cannonlake/acpi/northbridge.asl b/src/soc/intel/cannonlake/acpi/northbridge.asl
index 0e8a281..346efdb 100644
--- a/src/soc/intel/cannonlake/acpi/northbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/northbridge.asl
@@ -15,8 +15,327 @@
* GNU General Public License for more details.
*/
- Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
- Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
- Name (_SEG, Zero) // _SEG: PCI Segment
- Name (_ADR, Zero) // _ADR: Address
- Name (_UID, Zero) // _UID: Unique ID
+#include <soc/iomap.h>
+#define BASE_32GB 0x800000000
+#define SIZE_16GB 0x400000000
+
+Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
+Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
+Name (_SEG, Zero) // _SEG: PCI Segment
+Name (_ADR, Zero) // _ADR: Address
+Name (_UID, Zero) // _UID: Unique ID
+
+Device (MCHC)
+{
+ Name (_ADR, 0x00000000)
+
+ OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
+ Field (MCHP, DWordAcc, NoLock, Preserve)
+ {
+ Offset(0x40), /* EPBAR (0:0:0:40) */
+ EPEN, 1, /* Enable */
+ , 11,
+ EPBR, 20, /* EPBAR [31:12] */
+
+ Offset(0x48), /* MCHBAR (0:0:0:48) */
+ MHEN, 1, /* Enable */
+ , 14,
+ MHBR, 17, /* MCHBAR [31:15] */
+
+ Offset(0x60), /* PCIEXBAR (0:0:0:60) */
+ PXEN, 1, /* Enable */
+ PXSZ, 2, /* PCI Express Size */
+ , 23,
+ PXBR, 6, /* PCI Express BAR [31:26] */
+
+ Offset(0x68), /* DMIBAR (0:0:0:68) */
+ DIEN, 1, /* Enable */
+ , 11,
+ DIBR, 20, /* DMIBAR [31:12] */
+
+ Offset (0xa0), /* Top of Used Memory */
+ TOM, 64,
+
+ Offset (0xa8), /* Top of Upper Used Memory */
+ TUUD, 64,
+
+ Offset (0xbc), /* Top of Low Used Memory */
+ TLUD, 32,
+ }
+}
+
+Name (MCRS, ResourceTemplate ()
+{
+ /* Bus Numbers */
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100)
+
+ /* IO Region 0 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8)
+
+ /* PCI Config Space */
+ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ /* IO Region 1 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ EntireRange,
+ 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300)
+
+ /* VGA memory (0xa0000-0xbffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000)
+
+ /* OPROM reserved (0xc0000-0xc3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xc4000-0xc7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xc8000-0xcbfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xcc000-0xcffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xd0000-0xd3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xd4000-0xd7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xd8000-0xdbfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xdc000-0xdffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xe0000-0xe3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xe4000-0xe7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xe8000-0xebfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xec000-0xeffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+ 0x00004000)
+
+ /* System BIOS (0xf0000-0xfffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+ 0x00010000)
+
+ /* PCI Memory Region (TLUD - 0xdfffffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
+ 0xE0000000,,, PM01)
+
+ /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000, 0x10000, 0x1ffff, 0x00000000,
+ 0x10000,,, PM02)
+
+ /* PCH reserved resource (0xfc800000-0xfe7fffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, 0x00000000,
+ PCH_PRESERVED_BASE_SIZE)
+
+ /* TPM Area (0xfed40000-0xfed47fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000,
+ 0x00008000)
+})
+
+Method (_CRS, 0, Serialized)
+{
+ /* Find PCI resource area in MCRS */
+ CreateDwordField (^MCRS, ^PM01._MIN, PMIN)
+ CreateDwordField (^MCRS, ^PM01._MAX, PMAX)
+ CreateDwordField (^MCRS, ^PM01._LEN, PLEN)
+
+ /*
+ * Fix up PCI memory region
+ * Start with Top of Lower Usable DRAM
+ */
+ Store (^MCHC.TLUD, PMIN)
+ Add (Subtract (PMAX, PMIN), 1, PLEN)
+
+ /* Patch PM02 range based on Memory Size */
+ CreateQwordField (^MCRS, ^PM02._MIN, MMIN)
+ CreateQwordField (^MCRS, ^PM02._MAX, MMAX)
+ CreateQwordField (^MCRS, ^PM02._LEN, MLEN)
+
+ Store (^MCHC.TUUD, Local0)
+
+ If (LLessEqual (Local0, BASE_32GB)) {
+ Store (BASE_32GB, MMIN)
+ Store (SIZE_16GB, MLEN)
+ } Else {
+ Store (0, MMIN)
+ Store (0, MLEN)
+ }
+ Subtract (Add (MMIN, MLEN), 1, MMAX)
+
+ Return (^MCRS)
+}
+
+Name (EP_B, 0) /* to store EP BAR */
+Name (MH_B, 0) /* to store MCH BAR */
+Name (PC_B, 0) /* to store PCIe BAR */
+Name (PC_L, 0) /* to store PCIe BAR Length */
+Name (DM_B, 0) /* to store DMI BAR */
+
+/* Get MCH BAR */
+Method (GMHB, 0, Serialized)
+{
+ If (LEqual (MH_B, 0)) {
+ ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B)
+ }
+ Return (MH_B)
+}
+
+/* Get EP BAR */
+Method (GEPB, 0, Serialized)
+{
+ If (LEqual (EP_B, 0)) {
+ ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B)
+ }
+ Return (EP_B)
+}
+
+/* Get PCIe BAR */
+Method (GPCB, 0, Serialized)
+{
+ If (LEqual (PC_B, 0)) {
+ ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B)
+ }
+ Return (PC_B)
+}
+
+/* Get PCIe Length */
+Method (GPCL, 0, Serialized)
+{
+ If (LEqual (PC_L, 0)) {
+ ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L)
+ }
+ Return (PC_L)
+}
+
+/* Get DMI BAR */
+Method (GDMB, 0, Serialized)
+{
+ If (LEqual (DM_B, 0)) {
+ ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B)
+ }
+ Return (DM_B)
+}
+
+/* PCI Device Resource Consumption */
+Device (PDRC)
+{
+ Name (_HID, EISAID ("PNP0C02"))
+ Name (_UID, 1)
+
+ Name (BUF0, ResourceTemplate ()
+ {
+ /* MCH BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.48h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x08000, MCHB)
+
+ /* DMI BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.68h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x01000, DMIB)
+
+ /* EP BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.40h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
+
+ /* PCI Express BAR _BAS and _LEN will be updated in
+ * _CRS below according to B0:D0:F0:Reg.60h
+ */
+ Memory32Fixed (ReadWrite, 0, 0, PCIX)
+
+ /* VTD engine memory range.
+ */
+ Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, 0x00004000)
+
+ /* FLASH range */
+ Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) /* 16MB */
+
+ /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
+ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
+
+ /* HPET address decode range */
+ Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
+ })
+
+ Method (_CRS, 0, Serialized)
+ {
+ CreateDwordField (BUF0, ^MCHB._BAS, MBR0)
+ Store (\_SB.PCI0.GMHB (), MBR0)
+
+ CreateDwordField (BUF0, ^DMIB._BAS, DBR0)
+ Store (\_SB.PCI0.GDMB (), DBR0)
+
+ CreateDwordField (BUF0, ^EGPB._BAS, EBR0)
+ Store (\_SB.PCI0.GEPB (), EBR0)
+
+ CreateDwordField (BUF0, ^PCIX._BAS, XBR0)
+ Store (\_SB.PCI0.GPCB (), XBR0)
+
+ CreateDwordField (BUF0, ^PCIX._LEN, XSZ0)
+ Store (\_SB.PCI0.GPCL (), XSZ0)
+
+ Return (BUF0)
+ }
+}
+
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
index 698c510..1538ab2 100644
--- a/src/soc/intel/cannonlake/include/soc/iomap.h
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -69,6 +69,7 @@
#define PTT_TXT_BASE_ADDRESS 0xfed30800
#define PTT_PRESENT 0x00070000
+#define VTD_BASE_ADDRESS 0xFED90000
/*
* I/O port address space
*/
To view, visit change 21756. To unsubscribe, visit settings.